Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002 Donnamaie E. White



Last Edit July 22, 2001

eLearning - Next Best Thing

When I first composed this text, back in the early 1990s, little did I realize how much the industry would leap forward. None of us were prepared for the advance of the Internet, although e-mail had been with the engineering community since the 1960s and FTP had been in use since at least that time. HTML burst upon the scene and several of us clicked on the concept of "living" classrooms on the web almost instantly. In 2001, Harvard put its entire curriculum on-line (for free). Cadence has put all of its technical training classes on-line (for a fee). Synopsys has begun to put its technical training on the web.

The industry has spawned expensive-to-produce CD ROM training, which has not been widely accepted, page-turners (PowerPoint presentations with/without audio and with/without video assist, "live" webcasts or update training, and fully-integrated, true computer-based instruction.

The goal is to have "living" technical material that can be updated faster than the two-year cycle for a technical book or the six-month cycle of a technical journal. The web is immediate.

This author has just completed the conversion of the Synopsys Advanced Chip Synthesis 3-day lecture-lab Workshop into the Advanced Chip Synthesis eLearning Workshop, hosted at Vitalect. This is the first of several planned course conversions. The workshops will still be available in ILT form (Instructor Led Training) as well.

There is a free on-line Advanced Chip Synthesis Demo featuring one of the workshop Units. You can view the demo at Vitalect but your browser must be configured with RealAudio and Flash for proper display of animations and to hear the audio scripts. Vitalect features a "Set-Up" page to help you.

Training Classes - Historical Review

ASIC, library and EDA vendors offer training classes where the array product and its peripheral requirements for design submission are presented in intense two to five day seminars and workshops. Because of the structure of a class, the array vendor can attempt to ensure that important issues are discussed or at least brought to the attention of the designers. This reduces the problems that could occur during the acceptance review of the design submission which shortens the first-time design cycle.

AMCC - Applied Micro Circuits Corporation - offered a three-day array design class and a two-day workshop workstation lab class to its customers. This class was taught for seven years, using the same methodology for a range of evolving products: Bipolar Q700 Series, Q1500, QH1500, Q3500 Series, Q5000 Series, Q20000 Series; CMOS Q6000 Series, Q6000A Series, Q9000 Series; BiCMOS Q14000 Series; and Q24000 Series.

The workstations covered included the Daisy Logician (now obsolete) Dazix SUN, VALID SCALD (now obsolete), Valid SUN and Mentor on Apollo. Simulators include Tegas 5 (discontinued at AMCC), Lasar 6 and Verilog. The seminar was also taught at UCSD - University of California at San Diego - as an extension graduate engineering class with credit.

The range of series and the variability of the platforms and tools listed for just one vendor demonstrates some of the problems associated with maintaining currency.

Vendor-Independent Training - the Design Flow

With the range of technologies and array families within any technology and the number of workstations, platforms and simulators that support them, a basic design methodology was developed at AMCC to ensure a successful design the first time.

This design flow is reflected in the wide variety of design tools and customer education classes offered at Synopsys and Cadence, the two biggest EDA firms. At this moment Synopsys is the industry leader in synthesis tools (Design Compiler, Module CompilerBehaviorial Compiler, Designware Foundation, RTL Analyzer, etc. ) and Cadence is the leader in Place and Route tools (Gate Ensemble, Silicon Ensemble).

The same flow is represented in the design-reuse concept supported by Synopsys and other companies. The flow is used with little variation for the design of a full chip (core and I/O) and for the design of an IP module (core-only).

Structured design works.

The methods have been developed and tested with hundreds of designs. Any problems seen on submissions and prototypes can usually be traced back to some violation of the stated design methodology.

In addition to AMCC and its arrays and the Synopsys CBA Design System, design manuals from other vendors were obtained and reviewed to verify that the basic approach is generic, i.e., technology and vendor independent.

Once a structured design methodology was developed, it was imperative that the presentation be consistent across several instructors. Class notes, usually in the form of slides or overheads, are merely topical outlines and suppliments. Few instructors last long if everything is written on the overhead and instruction is a "reading of the screen". The usual procedure is to keep key words and phrases on the screen and the instructor then speaks "off the cuff".

This approach is acceptable for most subjects. ASIC design is so complex and encompassing an issue that the class content can be driven by active students so that it emphasizes those areas questioned and de-emphasizes the rest. Classes will therefore vary in the depth of topics covered depending on the students in attendance.

About This Text

An improvement to the process is a text book that can survive the evolving technologies and changing equipment. This text is an attempt to capture the verbal lecture used by the AMCC/UCSD instructor for this course to provide consistency for the classroom and for those who choose to be self-taught. It does not try to duplicate what can be found in the design manuals per se beyond using design examples. The student cum reader is always referenced to the most current design manual and datasheet for the array or array series or vendor support software of interest.

This text will present the basic structured design flow, show how various steps interconnect, how they may be performed and provide checklists of items that should be known prior to design start. It is designed to support any vendor and any array.

For those who were taking the class for credit, chapter exercises were provided to allow the students to perform exercises using the equipment and materials of interest to them. At the time, schematic-capture was the methodology; today we have VHDL and Verilog. Daisy, Mentor and Valid workstations centered on shcematic capture are no longer found in most engineering environments. The SUN workstation, the NT platform, HP and LINUX are the modes of operation today using advanced software tools to complete the tasks formerly done by hand.


Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com