Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002 Donnamaie E. White

 

Introduction

Last Edit July 22, 2001


Design Tools - [2001]

In the 1990s the industry began to shift to EDA tools to handle the increased complexity of the ASIC designs. Any reasonable engineer can handle a design of up to 30,000 gates. When 6 million gates are involved, it would take multiple engineers years to complate one design.

By the 1990s designs shifted from schematic capture, with the engineeer selecting the appropriate macros from a library, to HDL code. VHDL is currently used in Europe and Verilog is currently used in the United States.

Design Tools - [1990s]

To perform a logical circuit design for an array-based circuit, the designer may choose between schematic capture, direct netlist creation, and the use of behavorial languages such as HDL and VHDL. Netlist generation as was done using Tegas is too tedious an approach for ASIC-based circuits past a minimal size. Netlist generation via a behavioral language or from schematic capture is the more usual approach.

Translation programs exist to move a netlist in one format to a netlist in another format. The industry is still trying to expand the idea of EDIF, a common netlist that would allow input to any simulator and any placement system.

For example: Verilog to Mentor translation is now possible using a Verilog netlist to create Mentor schematics. (Back-generation of schematics will remain a necessary step in spite of the push for behavioral descriptions as the preferred design tool.)

Once an acceptable netlist has been generated by whatever means, the designer needs to check or verify that the design rules have not been violated. When the circuit is certified as acceptable and buildable, the circuit must be simulated according to the design submission requirements of the chosen vendor. The simulation must be checked. The design must be documented.

Simulations involve control programs, stimulus generation, annotation delay files and descriptions. AC test analysis requires additional documentation. Which simulator can be used, and whether any timing verifier or other tools are available, is limited to what the array vendor supports.

The simulation output files must be formatted according to vendor rules to allow the generation of test vectors. These will be transferred to the placement software and to test-generation software. A submission may include dozens of files that must be tracked, controlled for revision level and managed to verify that the design submitted to the vendor is the one intended to be submitted. And yes, errors do occur.

Framework Systems

Framework systems are under development as the means of alleviating the design management problem but they are in their infancy and industry sages are predicting at least five years before they meet any goals. Further, those developing framework systems disagree about those goals.

There are four basic functions of a frame work agreed upon:

  • integration of design tools
  • provide a common user interface
  • manage the design data and
  • manage the design process.

The integration of design tools includes tools from non-framework vendors. Allowing access to different design tools requires that the interface to those tools be reasonably similar and easy to use. (The Macintosh computers have proven the merit of similar and easy interface to tools and common databases.)

Array Selection as the First Task

Whatever the framework systems end up providing, the basic design flow that exists today will remain intact. The first and most difficult task of array selection will not change, nor will the basic goals of the current design methodology.

It is the ease of satisfying those goals that will change.

The process of selecting an implementation for a circuit involves two basic decision processes.

  • First, a decision must be made on the technology that will satisfy the design criteria for power and speed.
  • Second, a selection must be made from the components (arrays, macro, IP, I/O, etc.) available within those technologies.

Even with all the changes made in software tools, these two key items remain unchanged. Choose the process, which defines the technology, and then choose the components, for even with high-level synthesis, the astutue designer can "guide" the software to a better solution. The software (Synopsys, Cadence, Avant! are the big three) is chosen by the designing group with input from the selected foundry as to the product design flow.


Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com