Logic Design for Array-Based Circuits
Copyright © 1996, 2001, 2002 Donnamaie E. White
Timing Analysis for Arrays
Last Edit July 22, 2001
Example Equations for Extrinsic Loading -Internal Nets
Loading delays may be computed for Front-Annotation analysis by the general equation:
The k-Factors are the conversion factors for changing load units into time units. These k-Factors are expressed in ns/LU. The load units are computed for electrical fan-out, net metalization and electrical wire-OR loads. The k-Factors may be assumed to be identical for Front-Annotation estimation. If the array does not allow wire-OR structures, the equation reduces to:
Lnet - Front-Annotation
Lnet is the statistical wire load taken from the Front-Annotation Statistical Wire Load table supplied by the vendor or from an equation that is supplied by the vendor, using the number of physical pins in the net minus 1 as an index. Lnet is expressed in load units. This load may also be specified through graphs.
For Front-Annotation, Lnet tables are derived from empirical measurement of hundreds of nets of equal size in actual circuits on the same array and the resulting 50% point in the normal distribution (the median) is used as the table entry. This means that 50% of the net delays computed with this number will be equal to or smaller than this number and 50% will be equal to or larger than the computed number.
When an array is preliminary, not many circuits will have been tested or measured. This means that the Front-Annotation values are estimates of expected delays. The errors could be in either direction.
For any array, Front-Annotation accuracy decreases with net size.
Critical paths that are pre-placed or given a higher priority in place and route operations than the rest of the circuit can be kept within the Front-Annotation limits. Other circuits that are not critical will have longer metal lengths.
A reasonable number of paths in the circuit can be prioritized, with the allowed number a function of other the placement restrictions for the circuit, cell utilization and internal pin count. A limit - on the number of pre-placed and priority routed paths - of 20% is satisfactory for most circuits.
Preplacement should not be considered as a solution to a timing problem. It is available as an aid, depending on other placement considerations.
The loading that a typical macro presents to its driving source is typically one load for bipolar arrays and higher for BiCMOS arrays. Some vendors specify fan-in in tabular form with other specification data, or indicate a general rule.
Some macros look as if they present two or more loads to their driving sources when they do not. The graphic representation is a logical picture of the function, not a physical representation of how the function is constructed.
Fan-Out - Lfo
Fan-in affects the electrical loading presented to the driving macro. The electrical fan-out load count may be higher than the physical fan-out load count. For example, a pin with a fan-in of 2 counts as two electrical loads in Lfo and one physical pin when looking up Lnet.
Fan-out violations or fan-out in excess of derated levels should have been checked during the design review of the circuit. Derated fan-out limits are used by the AMCCERC software when performing fan-out load limit violation checking. If a fan-out load is found to be excessive, the circuit must be corrected before proceeding with the timing analysis.
Lfo is the sum of all fan-out loads. This is the sum of all electrical fan-out loads - the sum of the fan-in for each pin connected to the net. Lfo is expressed in load units. The load a macro presents to a driving macro is part of the macro specifications.
Wire-OR - Lwo
For arrays that allow wire-ORs, Lwo is W * (n-1) where W is the wire-OR load factor for the array and n is the wire-OR size. Lwo is expressed in load units. This term only exists for those arrays that allow a wire-OR.
Not all arrays in all technologies allow the use of the wire-OR. If it is legal for the array, the presence of a wire-OR in a net will affect both the electrical and the physical loading in the net.
Wire-ORing two outputs will not increase the fan-out load limit in the bipolar arrays as it would have in a CMOS array. AMCC Q5000 arrays, which allow wire-ORs, power-down the additional current sources by way of conditional geometry software.
Load units for the Q5000 wire-OR macros are shown in Table 5-2.
Table 5-2 Q5000 Wire-Or Loading (Lwo)