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This book is the Electronic Engineers' comprehensive VHDL/Verilog modeling guide for ASIC and FPGAs
This book describes, and shows by practical example, how to design ASIC and FPGA devices using the two industry standard hardware description languages, VHDL and Verilog. The emphasis is on RTL modeling using synthesis within a top-down design methodology.
With this book learn how to:
- make chip design easier,
- improve your design productivity,
- design efficient synthesizable models,
- write good HDL test harnesses,
- acquire good design and modeling practices.
The author's straightforward facts take you from the basics of ASIC and FPGA design all the way though the most complex HDL applications. He makes understanding HDL modeling easy through his collection of complete graphical model descriptions, practical planning and helpful tips.
Electronic Engineers and students will find this complete VHDL/Verilog modeling guide to be an essential addition to their technical resources.
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