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The Art of Verification with VERA
List Price: $88.95
Online Price: $88.95
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Perfect
437 Pages
Published by Verification Central
Date Published: 08/2001
ISBN: 097119940X
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Table of Contents
- Chapter 1: Introduction to Verification
- Introduction to ASIC Design
- The ASIC Design Flow
- What Is Verification?
- Functional Verification Flow
- What Does the Testbench Do?
- Problems of Verification
- Hardware Verification Languages (HVLs)
- Chapter 2: Developing Verification Strategies
- Ethernet Switch Example
- Creating the Test Plan
- Test Generation Schemes
- Transactors
- Logging and Error Checking
- Formal Verification
- Chapter 3: Applying the Strategies to the Ethernet
MAC
- Ethernet Media Access Controller Specification
- Identifying the Testbenches
- Identifying the Test Cases
- Test Generation Policies
- Transactors
- Monitors
- Logging and Error Checking
- Summary
- Chapter 4: Vera Programming Constructs
- Program Structure
- Numbers and Data Types
- Operators and Expressions
- Control Structures
- Functions and Tasks
- Arrays and Associative Arrays
- Strings
- File I/O
- A Complex Program: A CPU
- Conclusion
- Chapter 5: RTL Ports and Interfaces in Vera
- Event Versus Cycle-Based Simulation
- Interfacing With a Simple Design: Multiport RAM
- Dealing With Multiple Clocks and Multiple Interfaces
- Interface Signal Types
- Interface Architecture
- Automatic Template Generation
- Stimulus and Response
- Virtual Ports and Binds
- Running a Vera Program With a Simulator
- Guidelines and Techniques
- The Complete Testbench Development Flow
- MAC Port Definition
- Conclusion
- Chapter 6: Creating Concurrency in Vera
- fork/join Construct
- Shadow Variables
- Mailboxes
- Semaphores
- Regions
- Events
- More Thread Control
- Summary
- Chapter 7: Objects in Vera: Modeling Higher Levels
of Abstraction
- What Is an Object?
- Objects in Vera
- Identifying Classes and Methods
- Summary
- Object-Oriented Keywords
- Chapter 8: Automatic Stimulus Generation and Randomized
Testing in Vera
- Stimulus Generation
- Stimulus Generation for MAC
- Vera Support for Randoms
- Types of Constraints
- Pre- and Post-Randomize
- Packing and Unpacking
- Test Creation Strategies
- Overview
- Summary
- Chapter 9: Object Extension and Polymorphism
in Vera
- Introduction to Inheritance and Polymorphism
- Extending a Class in Vera
- Application of Inheritance
- Polymorphism
- Guidelines for Using Inheritance and Polymorphism
- Conclusion
- Chapter 10: Building Transactors and Stubs
- Transactors
- Interfacing With the Stimulus
- MAC Transactor: Interfacing With the Design
- Extending the Functionality of the Transactors
- Instantiating the Extended Class
- Conclusion
- Chapter 11: Generating Stimulus
- Generation Policies
- Interfaces to Other Components of the testbench
- Components of the Stimulus Generator
- Sample Code
- Main Program
- Providing for Corner Cases
- Summary
- Chapter 12: Models, Monitors, and Result Checking
- Result Checking
- Monitoring Strategies
- Example MAC Testbench Overview
- MAC Monitor Implementation
- MAC Packet Monitoring Issues
- Host Monitor
- MII Monitor
- Instantiating the Monitors
- Summary
- Chapter 13: How Do I Know I Am Done?
- Bug Rate
- Coverage
- Regressions and Regressibility
- Summary
- Chapter 14: Debugging Testbench and RTL
- Avoidance Through Preventive Programming
- Preventive Programming Styles
- The Debugging Process
- Key debugging issues
- Summary
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