B.4  Verilog HDL LRM

B.4  Verilog HDL LRM

An important feature of Verilog is the ability to extend tools by writing your own code and integrating it with a Verilog-based tool. For example, the following code calls a user-written system task, :

initial (a_reg);

Here is the C program, hello.c , that prints the full hierarchical name of the instance in which the Verilog code containing the call to is located:

#include "veriuser.h"

#include "acc_user.h"

int hello()

{ handle mod_handle; char *full_name; acc_initialize();

mod_handle = acc_handle_tfarg(1);

io_printf("Hello from: %s ", acc_fetch_fullname(mod_handle));

acc_close(); }

The details of how to compile and link your program with the Verilog executable depend on the particular tool; the names, functions, and parameters of ACC routines, the header files, veriuser.h and acc_user.h (most companies include these with their Verilog products), as well as older TF routines and the newer VPI routines are described in detail in Sections 17–23 of the 95 LRM.

Annex F of the 95 LRM describes widely used Verilog system tasks and functions that are not required to be supported as part of IEEE Std 1364-1995. Table B.3 summarizes these tasks and functions. Annex G of the 95 LRM describes additional compiler directives that are not part of IEEE Std 1364-1995 and are not often used by ASIC designers. Two directives, `default_decay_time and `default_trireg_strength , are used to model charge decay and the strength of high-impedance trireg nets. Four more compiler directives: `delay_mode_distributed , `delay_mode_path , `delay_mode_unit, and `delay_mode_zero are used to specify the delay mode for modules.

TABLE B.3  System tasks and functions (not required in IEEE Std 1364-1995).

( net, [ net_is_forced, number_of_01x_drivers, number_of_0_drivers,
number_of_1_drivers, number_of_x_drivers ] ) ;

Returns a 0 if there is no more than one driver on the net and returns a 1 otherwise (indicating contention).

( mem_element ) ; // Drive a pattern from an indexed memory.

Example: assign {i1, i2, i3, i4} = ( mem [ index ] )

("filename"); // Allows input from file rather than terminal.

[ ( "filename" ) ] ; ; // Enable/disable key file in interactive mode.

[ ( hierarchical_name ) ] ; // List current or specified object.

[ ( "filename" ) ] ; ; // Enable/disable log file for standard output.

[ ( stop_value [ , reset_value , [ diagnostics_value ] ] ) ] ; // Reset time.

; // Count the number of resets.

; // Pass information prior to reset to simulation after reset.

( "file_name" ) ; // Save simulation for later restart.

( "file_name" ) ; // Restart simulation from saved file.

( "incremental_file_name" ) ; // Save only changes since last

( hierarchical_name ) ; // Convert to time units of invoking module.

( hierarchical_name ) ; // Sets the specified level of hierarchy as current scope.

[ ( n ) ]; // Show scope (n = none or zero) else show all items below scope.

[ ( list_of_variables ) ] ; // Show status of scope or specified variables.

( mem_name , start_address , finish_address , string { , string } ) ;

( mem_name , start_address , finish_address , string { , string } ) ;

Load data into mem_name from character string (same format as /h ).


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