17.8 References

17.8  References

Page numbers in brackets after a reference indicate its location in the chapter body.

Banerjee, P. 1994. Parallel Algorithms for VLSI Computer-Aided Design Applications. Englewood Cliffs, NJ: Prentice-Hall, 699 p. ISBN 0130158356. TK7874.75.B36. [ reference location ]

Barke, E. 1988. “Line-to-ground capacitance calculation for VLSI: A comparison.” IEEE Transactions on Computer-Aided Design, Vol. 7, no. 2, pp. 295–298. Compares various equations for line to ground capacitance and finds the van der Meijs and Fokkema equation the most accurate. [ reference location ]

Black, J. R. 1969. “Electromigration failure modes in aluminum metallization for semiconductor devices.” Proceedings of the IEEE, Vol. 57, no. 9, pp. 1587–1594. Describes mechanism and theory of electromigration. Two failure modes are discussed: dissolution of silicon into aluminum, and condensation of aluminum vacancies to form voids. Electromigration failures in aluminum become important (less than 10 year lifetime) at current densities greater than 50 kA/sq.cm and temperatures greater than 150 °C. [ reference location ]

Cadence. 1990. “Gate Ensemble User Guide.” Product Release 2.0. Describes gate-array place-and-route software. The algorithms for timing-driven placement are described in A. H. Chao, E. M. Nequist, and T. D. Vuong, “Direct solution of performance constraints during placement,” in Proceedings of the IEEE Custom Integrated Circuits Conference, 1990. The delay models for timing analysis are described in “Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation,” in P. R. O’Brien and T. L. Savarino, in Proceedings of the International Conference on Computer-Aided Design, 1989. [ reference location ]

Cheng, C.-K., et al. 1992. “Geometric compaction on channel routing.” IEEE Transactions on Computer-Aided Design, Vol. 11, no. 1, pp. 115–127. [ reference location ]

Chowdhury, S., and J. S. Barkatullah. 1988. “Current estimation in MOS IC logic circuits.” In Proceedings of the International Conference on Computer-Aided Design. Compares estimates for transient current flow for CMOS logic gates. Algebraic models give results close to SPICE simulations. The rest of the paper discusses the calculation of static current flow for nMOS logic gates. A model for static current for CMOS gates is developed in terms of the nMOS models.

D’Heurle, F. M. 1971. “Electromigration and failure in electronics: an introduction.” Proceedings of the IEEE, Vol. 59, no. 10, pp. 1409–1417. Describes the theory behind electromigration in bulk and thin-film metals. Includes some experimental results and reviews work by others. Describes the beneficial effects of adding copper to aluminum metallization. [ reference location ]

Friedman, E. G. (Ed.). 1995. Clock Distribution Networks in VLSI Circuits and Systems. New York: IEEE Press, ISBN 0780310586. TK7874.75.C58. [ reference location ]

Gildenblat, G. S., and G. P. Schwartz (Eds.). 1991. Metallization: Performance and Reliability Issues for VLSI and ULSI. Bellingham, WA: SPIE, the International Society for Optical Engineering, 159 p. ISBN 0819407275. TK7874.M437. [ reference location ]

Glendinning, W. B., and J. N. Helbert, (Eds.). 1991. Handbook of VLSI Microlithography : Principles, Technology, and Applications. Park Ridge, NJ: Noyes Publications, 649 p. ISBN 0815512813. TK7874.H3494. [ reference location ]

Goel, A. K. 1994. High Speed VLSI Interconnections: Modeling, Analysis, and Simulation. New York: Wiley-Interscience, 622 p. ISBN 0471571229. TK7874.7.G63. 21 pages of references. [ reference location ]

Hashimoto, A., and J. Stevens. 1971. “Wire routing by optimal channel assignment within large apertures.” In Proceedings of the 8th Design Automation Workshop, pp. 155–169. [ reference location ]

Hu, T. C., and E. S. Kuh (Eds.). 1983. VLSI Circuit Layout: Theory and Design. New York: IEEE Press. ISBN 0879421932. TK7874 .V5573. Contains 26 papers divided into six chapters; Part 1: Overview (a paper written for this book with 167 references on layout and routing); Part II: General; Part III: Wireability, Partitioning and Placement; Part IV: Routing; Part V: Layout Systems; Part VI: Module Generation. [ reference location ]

Joobbani, R. 1986. An Artificial Intelligence Approach to VLSI Routing. Hingham, MA: Kluwer. ISBN 0-89838-205-X. TK7874.J663. Ph.D thesis on the development and testing of an intelligent router including an overview of the detailed routing problem and the Lee and “greedy” algorithms. [ reference location ]

Kahng, A. B., and G. Robins. 1995. On Optimal Interconnections for VLSI. Norwell, MA: Kluwer. ISBN 0-7923-9483-6. TK7874.75.K34. Extensive reference work on timing-driven detailed routing. [pp. 953, 956]

Lengauer, T. 1990. Combinatorial Algorithms for Integrated Circuit Layout. Chichester, England: Wiley. ISBN 0-471-92838-0. TK7874.L36. Background: Introduction to circuit layout; Optimization problems; Graph algorithms; Operations research and statistics. Combinatorial layout problems: The layout problem; Circuit partitioning; Placement, assignment, and floorplanning; Global routing and area routing; Detailed routing; Compaction. 484 references. [ reference location ]

Nakhla, M. S., and Q. J. Zhang (Eds.). 1994. Modeling and Simulation of High Speed VLSI Interconnects. Boston: Kluwer, 106 p. ISBN 0792394410. TK7874.75.M64. [ reference location ]

Murarka, S. P. 1993. Metallization: Theory and Practice for VLSI and ULSI. Stoneham, MA: Butterworth-Heinemann, 250 p. ISBN 0-7506-9001-1. TK7874.M868. Includes chapters on metal properties; crystal structure; electrical and mechanical properties; diffusion and reaction in thin metallic films; deposition method and techniques; pattern definition; packaging applications; reliability. [ reference location ]

Najm, F. N. 1994. “A survey of power estimation techniques in VLSI circuits.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 2, no. 4, pp. 446–55. 43 references. [ reference location ]

O’Brien, P. R., and T. L. Savarino. 1989. “Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation.” In Proceedings of the International Conference on Computer-Aided Design, pp. 512–515. Describes SPF PI segment model. [p reference location , 974 ].

Ohtsuki, T. (Ed.). 1986. Layout Design and Verification. New York: Elsevier Science, ISBN 0444878947. TK7874.L318. Includes nine papers on CAD tools and algorithms: “Layout strategy, standardisation, and CAD tools,” Ueda, Kasai, and Sudo; “Layout compaction,” Mylynski and Sung; “Layout verification,” Yoshida; “Partitioning, assignment and placement,” Goto and Matsuda; “Computational complexity of layout problems,” Shing and Hu; “Computational and geometry algorithms,” Asano, Sato, and Ohtsuki; an excellent survey and tutorial paper by M. Burstein — “Channel routing;” “Maze-running and line-search algorithms,” a good, easily readable paper on detailed routing by Ohtsuki; and a more mathematical paper, “Global routing,” by Kuh and Marek-Sadowska. [pp. 932, 957]

Pillage, L., et al. 1994. Electronic Circuit and System Simulation Methods. New York: McGraw-Hill, 392 p. ISBN 0-07-050169-6. TK7874.P52. [ reference location ]

Preas, B. T., and M. J. Lorenzetti. 1988. Physical Design Automation of VLSI Systems. Menlo Park, CA: Benjamin-Cummings, 510 p. ISBN 0805304129. TK7874.P47. Chapters on: physical design automation; interconnection analysis, logic partitioning; placement, assignment and floorplanning; routing; symbolic layout and compaction; module generation and silicon compilation; layout analysis and verification; knowledge-based physical design automation; combinatatorial complexity of layout problems. [ reference location ]

Ravikumar, C. P. 1996. Parallel Methods for VLSI Layout Design. Norwood, NJ: Ablex, 195 p. ISBN 0893918288. TK7874.R39. [ reference location ]

Roy, K. 1993. “A bounded search algorithm for segmented channel routing for FPGA’s and associated channel architecture issues.” IEEE Transactions on Computer-Aided Design, Vol. 12, no. 11, pp. 1695–1704. [ reference location ].

Sait, S. M., and H. Youssef. 1995. VLSI Physical Design Automation, Theory and Practice. New York: IEEE Press/McGraw-Hill copublication, 426 p. ISBN 0-07-707742-3. TK7874.75.S24. Covers floorplanning, placement, and routing. [ reference location ]

Sakurai, T., and K. Tamaru. 1983. “Simple formulas for two- and three-dimensional capacitances.” IEEE Transactions on Electron Devices . Vol. 30, no. 2. [ reference location ]

Sapatnekar, S. S., and S.-M. Kang. 1993. Design Automation for Timing-Driven Layout Synthesis. Boston: Kluwer, 269 p. ISBN 0792392817. TK7871.99.M44.S37. 19 pages of references. [ reference location ]

Sarrafzadeh, M., and C. K. Wong. 1996. An Introduction to VLSI Physical Design. New York: McGraw-Hill, 334 p. ISBN 0070571945. TK7874.75.S27. 17 pages of references. [ reference location ]

Shenai, K. (Ed.). 1991. VLSI Metallization: Physics and Technologies. Boston: Artech House, 529 p. ISBN 0890065012. TK7872.C68.V58. [ reference location ]

Sherwani, N. A. 1993. Algorithms for VLSI Physical Design Automation. 2nd ed. Norwell, MA: Kluwer, 538 p. ISBN 0-7923-9294-9. TK874.S455. See also the first edition. [ reference location ]

Sherwani, N. A., et al. 1995. Routing in the Third Dimension: From VLSI Chips to MCMs. New York: IEEE Press. ISBN 0-7803-1089-6. TK7874.75.R68. Reviews two-layer and multilayer routing algorithms. Contains chapters on: graphs and basic algorithms; channel routing; routing models; routing algorithms for two- and three-layer processes and MCMs. [ reference location ]

Taylor, G., and G. Russell. (Eds.). 1992. Algorithmic and Knowledge Based CAD for VLSI. London: P. Peregrinus, 273 p. ISBN 086341267X. TK7874.A416. [ reference location ]

Veendrick, H. J. M. 1984. “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits.” IEEE Journal of Solid-State Circuits, Vol. 19, no. 4, pp. 468–473. [ reference location ]

Young, D., and A. Christou. 1994. “Failure mechanism models for electromigration.” IEEE Transactions on Reliability, Vol. 43, no. 2, pp. 186–192. A tutorial on electromigration and its relation to microstructure. [p reference location , 957]

Zobrist, G. W. (Ed.). 1994. Routing, Placement, and Partitioning. Norwood, NJ: Ablex, 293 p. ISBN 0893917842. TK7874.R677. [ reference location ]

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