Chapter start Previous page Next page 10.11 OperatorsTable 10.16 shows the predefined VHDL operators, listed by their (increasing) order of precedence [VHDL 93LRM7.2]. The shift operators and the xnor operator were added in VHDL93.
The left operand of the shift operators (VHDL93 only) is a onedimensional array with element type of BIT or BOOLEAN ; the right operand must be INTEGER . The adding operators ('+' and '') are predefined for any numeric type. You cannot use the adding operators on BIT or BIT_VECTOR without overloading. The concatenation operator '&' is predefined for any onedimensional array type. The signs ('+' and '') are defined for any numeric type. The multiplying operators are: '*' , '/' , mod , and rem . The operators '*' and '/' are predefined for any integer or floatingpoint type, and the operands and the result are of the same type. The operators mod and rem are predefined for any integer type, and the operands and the result are of the same type. In addition, you can multiply an INTEGER or REAL by any physical type and the result is the physical type. You can also divide a physical type by REAL or INTEGER and the result is the physical type. If you divide a physical type by the same physical type, the result is an INTEGER (actually type UNIVERSAL_INTEGER , which is a predefined anonymous type [VHDL LRM7.5]). Once againyou cannot use the multiplying operators on BIT or BIT_VECTOR types without overloading the operators. The exponentiating operator, '**' , is predefined for integer and floatingpoint types. The right operand, the exponent, is type INTEGER . You can only use a negative exponent with a left operand that is a floatingpoint type, and the result is the same type as the left operand. The unary operator abs (absolute value) is predefined for any numeric type and the result is the same type. The operators abs , '**' , and not are grouped as miscellaneous operators. Here are some examples of the use of VHDL operators: entity Operator_1 is end; architecture Behave of Operator_1 is begin process variable b : BOOLEAN; variable bt : BIT := '1'; variable i : INTEGER; variable pi : REAL := 3.14; variable epsilon : REAL := 0.01; variable bv4 : BIT_VECTOR (3 downto 0) := "0001"; variable bv8 : BIT_VECTOR (0 to 7); begin b := "0000" < bv4;  b is TRUE, "0000" treated as BIT_VECTOR. b := 'f' > 'g';  b is FALSE, 'dictionary' comparison. bt := '0' and bt;  bt is '0', analyzer knows '0' is BIT. bv4 := not bv4;  bv4 is now "1110". i := 1 + 2;  Addition, must be compatible types. i := 2 ** 3;  Exponentiation, exponent must be integer. i := 7/3;  Division, L/R rounded towards zero, i=2. i := 12 rem 7;  Remainder, i=5. In general:  L rem R = L((L/R)*R). i := 12 mod 7;  modulus, i=5. In general:  L mod R = L(R*N) for an integer N.  shift := sll  srl  sla  sra  rol  ror (VHDL93 only) bv4 := "1001" srl 2;  Shift right logical, now bv4="0100".  Logical shift fills with T'LEFT. bv4 := "1001" sra 2;  Shift right arithmetic, now bv4="0111".  Arithmetic shift fills with element at end being vacated. bv4 := "1001" ror 2;  Rotate right, now bv4="0110".  Rotate wraps around.  Integer argument to any shift operator may be negative or zero. if (pi*2.718)/2.718 = 3.14 then wait; end if;  This is unreliable. if (abs(((pi*2.718)/2.718)3.14)<epsilon) then wait; end if;  Better. bv8 := bv8(1 to 7) & bv8(0);  Concatenation, a left rotation. wait; end process; end; 1. The not operator is a logical operator but has the precedence of a miscellaneous operator. 2. Underline means "new to VHDL93." 




