There are no recent monographs or review articles on floorplanning modern ASICs with interconnect delay dominating gate delay. Placement is a much more developed topic. Perhaps the simplest place to dig deeper is the book by Preas and Lorenzetti that contains a chapter titled “Placement, assignment, and floorplanning”
[Preas and Karger, 1988]. The collection edited by Ohtsuki [
1986] contains a review paper by Yoshida titled “Partitioning, assignment, and placement.” Sangiovanni-Vincentelli’s review article [
1986] complements Ohtsuki’s edited book, but both are now dated. Sechen’s book  describes simulated annealing and its application to placement and chip-planning for standard cell and gate array ASICs. Part III of the IEEE Press book edited by Hu and Kuh [
1983] is a collection of papers on wireability, partitioning, and placement covering some of the earlier and fundamental work in this area. For a more recent and detailed look at the inner workings of floorplanning and placement tools, Lengauer’s [
1990] book on algorithms contains a chapter on graph algorithms and a chapter on placement, assignment, and floorplanning. Most of these earlier book references deal with placement before the use of timing as an additional objective. The tutorial paper by Benkoski and Strojwas [
1991] contains a number of references on performance-driven placement. Luk’s book [
1991] describes methods for estimating net delay during placement.
Papers and tutorials on all aspects of floorplanning and placement (with an emphasis on algorithms) are published in
IEEE Transactions on Computer-Aided Design.
The newest developments in floorplanning and placement appear every year in the
Proceedings of the ACM/IEEE Design Automation Conference
Proceedings of the IEEE International Conference on Computer-Aided Design
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