// comp_mux.v module comp_mux(a, b, outp); input [2:0] a, b; output [2:0] outp; function [2:0] compare; input [2:0] ina, inb; begin if (ina <= inb) compare = ina; else compare = inb; end endfunction assign outp = compare(a, b); endmodule
`timescale 1ns / 10ps module comp_mux_u (a, b, outp); input [2:0] a; input [2:0] b; output [2:0] outp; supply1 VDD; supply0 VSS; in01d0 u2 (.I(b[1]), .ZN(u2_ZN)); nd02d0 u3 (.A1(a[1]), .A2(u2_ZN), .ZN(u3_ZN)); in01d0 u4 (.I(a[1]), .ZN(u4_ZN)); nd02d0 u5 (.A1(u4_ZN), .A2(b[1]), .ZN(u5_ZN)); in01d0 u6 (.I(a[0]), .ZN(u6_ZN)); nd02d0 u7 (.A1(u6_ZN), .A2(u3_ZN), .ZN(u7_ZN)); nd02d0 u8 (.A1(b[0]), .A2(u3_ZN), .ZN(u8_ZN)); nd03d0 u9 (.A1(u5_ZN), .A2(u7_ZN), .A3(u8_ZN), .ZN(u9_ZN)); in01d0 u10 (.I(a[2]), .ZN(u10_ZN)); nd02d0 u11 (.A1(u10_ZN), .A2(u9_ZN), .ZN(u11_ZN)); nd02d0 u12 (.A1(b[2]), .A2(u9_ZN), .ZN(u12_ZN)); nd02d0 u13 (.A1(u10_ZN), .A2(b[2]), .ZN(u13_ZN)); nd03d0 u14 (.A1(u11_ZN), .A2(u12_ZN), .A3(u13_ZN), .ZN(u14_ZN)); nd02d0 u15 (.A1(a[2]), .A2(u14_ZN), .ZN(u15_ZN)); in01d0 u16 (.I(u14_ZN), .ZN(u16_ZN)); nd02d0 u17 (.A1(b[2]), .A2(u16_ZN), .ZN(u17_ZN)); nd02d0 u18 (.A1(u15_ZN), .A2(u17_ZN), .ZN(outp[2])); nd02d0 u19 (.A1(a[1]), .A2(u14_ZN), .ZN(u19_ZN)); nd02d0 u20 (.A1(b[1]), .A2(u16_ZN), .ZN(u20_ZN)); nd02d0 u21 (.A1(u19_ZN), .A2(u20_ZN), .ZN(outp[1])); nd02d0 u22 (.A1(a[0]), .A2(u14_ZN), .ZN(u22_ZN)); nd02d0 u23 (.A1(b[0]), .A2(u16_ZN), .ZN(u23_ZN)); nd02d0 u24 (.A1(u22_ZN), .A2(u23_ZN), .ZN(outp[0])); endmodule
`timescale 1ns / 10ps module comp_mux_o (a, b, outp); input [2:0] a; input [2:0] b; output [2:0] outp; supply1 VDD; supply0 VSS; in01d0 B1_i1 (.I(a[2]), .ZN(B1_i1_ZN)); in01d0 B1_i2 (.I(b[1]), .ZN(B1_i2_ZN)); oa01d1 B1_i3 (.A1(a[0]), .A2(B1_i4_ZN), .B1(B1_i2_ZN), .B2(a[1]), .ZN(B1_i3_Z; fn05d1 B1_i4 (.A1(a[1]), .B1(b[1]), .ZN(B1_i4_ZN)); fn02d1 B1_i5 (.A(B1_i3_ZN), .B(B1_i1_ZN), .C(b[2]), .ZN(B1_i5_ZN)); mx21d1 B1_i6 (.I0(a[0]), .I1(b[0]), .S(B1_i5_ZN), .Z(outp[0])); mx21d1 B1_i7 (.I0(a[1]), .I1(b[1]), .S(B1_i5_ZN), .Z(outp[1])); mx21d1 B1_i8 (.I0(a[2]), .I1(b[2]), .S(B1_i5_ZN), .Z(outp[2])); endmodule
`timescale 1 ns/100 ps module comp_mux_actel_o (a, b, outp); input [2:0] a, b; output [2:0] outp; wire n_13, n_17, n_19, n_21, n_23, n_27, n_29, n_31, n_62; CM8 I_5_CM8(.D0(n_31), .D1(n_62), .D2(a[0]), .D3(n_62), .S00(n_62), .S01(n_13), .S10(n_23), .S11(n_21), .Y(outp[0])); CM8 I_2_CM8(.D0(n_31), .D1(n_19), .D2(n_62), .D3(n_62), .S00(n_62), .S01(b[1]), .S10(n_31), .S11(n_17), .Y(outp[1])); CM8 I_1_CM8(.D0(n_31), .D1(n_31), .D2(b[2]), .D3(n_31), .S00(n_62), .S01(n_31), .S10(n_31), .S11(a[2]), .Y(outp[2])); VCC VCC_I(.Y(n_62)); CM8 I_4_CM8(.D0(a[2]), .D1(n_31), .D2(n_62), .D3(n_62), .S00(n_62), .S01(b[2]), .S10(n_31), .S11(a[1]), .Y(n_19)); CM8 I_7_CM8(.D0(b[1]), .D1(b[2]), .D2(n_31), .D3(n_31), .S00(a[2]), .S01(b[1]), .S10(n_31), .S11(a[1]), .Y(n_23)); CM8 I_9_CM8(.D0(n_31), .D1(n_31), .D2(a[1]), .D3(n_31), .S00(n_62), .S01(b[1]), .S10(n_31), .S11(b[0]), .Y(n_27)); CM8 I_8_CM8(.D0(n_29), .D1(n_62), .D2(n_31), .D3(a[2]), .S00(n_62), .S01(n_27), .S10(n_31), .S11(b[2]), .Y(n_13)); CM8 I_3_CM8(.D0(n_31), .D1(n_31), .D2(a[1]), .D3(n_31), .S00(n_62), .S01(a[2]), .S10(n_31), .S11(b[2]), .Y(n_17)); CM8 I_6_CM8(.D0(b[2]), .D1(n_31), .D2(n_62), .D3(n_62), .S00(n_62), .S01(a[2]), .S10(n_31), .S11(b[0]), .Y(n_21)); CM8 I_10_CM8(.D0(n_31), .D1(n_31), .D2(b[0]), .D3(n_31), .S00(n_62), .S01(n_31), .S10(n_31), .S11(a[2]), .Y(n_29)); GND GND_I(.Y(n_31)); endmodule
module allPads(padTri, padOut, clkOut, padBidir, padIn, padClk); output padTri, padOut, clkOut; inout padBidir; input [3:0] padIn; input padClk; wire [3:0] in; //compass dontTouch u* // asPadIn #(W, N, L, P) I (toCore, Pad) also asPadInInv // asPadOut #(W, N, L, P) I (Pad, frCore) // asPadTri #(W, N, S, L, P) I (Pad, frCore, OEN) // asPadBidir #(W, N, S, L, P) I (Pad, toCore, frCore, OEN) // asPadClk #(N, S, L) I (Clk, Pad) also asPadClkInv // asPadVxx #(N, subnet) I (Vxx) // W = width, integer (default=1) // N = pin number string, e.g. "1:3,5:8" // S = strength = {2, 4, 8, 16} in mA drive // L = level = {cmos, ttl, schmitt} (default = cmos) // P = pull-up resistor = {down, float, none, up} // Vxx = {Vss, Vdd} // subnet = connect supply to {pad, core, both} asPadIn #(4,"1:4","","none") u1 (in, padIn); asPadOut #(1,"5",13) u2 (padOut, d); asPadTri #(1,"6",11) u3 (padTri, in[1], in[0]); asPadBidir #(1,"7",2,"","") u4 (d, padBidir, in[3], in[2]); asPadClk #(8) u5 (clk, padClk); asPadOut #(1, "9") u6 (clkOut, clk); asPadVdd #("10:11","pads") u7 (vddr); asPadVss #("12,13","pads") u8 (vssr); asPadVdd #("14","core") u9 (vddc); asPadVss #("15","core") u10 (vssc); asPadVdd #("16","both") u11 (vddb); asPadVss #("17","both") u12 (vssb); endmodule
module PadTri (Pad, I, Oen); // active-low output enable parameter width = 1, pinNumbers = "", \strength = 1, level = "CMOS", externalVdd = 5; output [width-1:0] Pad; input [width-1:0] I; input Oen; assign #1 Pad = (Oen ? {width{1'bz}} : I); endmodule
module PadBidir (C, Pad, I, Oen); // active-low output enable parameter width = 1, pinNumbers = "", \strength = 1, level = "CMOS", pull = "none", externalVdd = 5; output [width-1:0] C; inout [width-1:0] Pad; input [width-1:0] I; input Oen; assign #1 Pad = Oen ? {width{1'bz}} : I; assign #1 C = Pad; endmodule
pc5o05 u2_2 (.PAD(padOut), .I(d)); pc5t04r u3_2 (.PAD(padTri), .I(in[1]), .OEN(in[0])); pc5b01r u4_3 (.PAD(padBidir), .I(in[3]), .CIN(d), .OEN(in[2])); pc5d01r u5_in_1 (.PAD(padClk), .CIN(u5toClkBuf[0]));
module dff(D,Q,Clock,Reset); // N.B. reset is active-low output Q; input D,Clock,Reset; parameter CARDINALITY = 1; reg [CARDINALITY-1:0] Q; wire [CARDINALITY-1:0] D; always @(posedge Clock) if (Reset!==0) #1 Q=D; always begin wait (Reset==0); Q=0; wait (Reset==1); end endmodule
module dff(D, Q, Clk, Rst); // new flip-flop for Viterbi decoder parameter width = 1, reset_value = 0; input [width - 1 : 0] D; output [width - 1 : 0] Q; reg [width - 1 : 0] Q; input Clk, Rst; initial Q <= {width{1'bx}}; always @ ( posedge Clk or negedge Rst ) if ( Rst == 0 ) Q <= #1 reset_value; else Q <= #1 D; endmodule
/* This is the top-level module, viterbi_ASIC.v */ module viterbi_ASIC (padin0, padin1, padin2, padin3, padin4, padin5, padin6, padin7, padOut, padClk, padRes, padError); input [2:0] padin0, padin1, padin2, padin3, padin4, padin5, padin6, padin7; input padRes, padClk; output padError; output [2:0] padOut; wire Error, Clk, Res; wire [2:0] Out; // core wire padError, padClk, padRes; wire [2:0] padOut; wire [2:0] in0,in1,in2,in3,in4,in5,in6,in7; // core wire [2:0] padin0, padin1,padin2,padin3,padin4,padin5,padin6,padin7; // Do not let the software mess with the pads. //compass dontTouch u* asPadIn #(3,"1,2,3") u0 (in0, padin0); asPadIn #(3,"4,5,6") u1 (in1, padin1); asPadIn #(3,"7,8,9") u2 (in2, padin2); asPadIn #(3,"10,11,12") u3 (in3, padin3); asPadIn #(3,"13,14,15") u4 (in4, padin4); asPadIn #(3,"16,17,18") u5 (in5, padin5); asPadIn #(3,"19,20,21") u6 (in6, padin6); asPadIn #(3,"22,23,24") u7 (in7, padin7); asPadVdd #("25","both") u25 (vddb); asPadVss #("26","both") u26 (vssb); asPadClk #("27") u27 (Clk, padClk); asPadOut #(1,"28") u28 (padError, Error); asPadin #(1,"29") u29 (Res, padRes); asPadOut #(3,"30,31,32") u30 (padOut, Out); // Here is the core module: viterbi v_1 (in0,in1,in2,in3,in4,in5,in6,in7,Out,Clk,Res,Error); endmodule
module Step_Time(clk, phase); input clk; output [2:0] phase; reg [2:0] phase; always @(posedge clk) begin phase <= 4'b0000; phase <= #1 4'b0001; phase <= #2 4'b0010; phase <= #3 4'b0011; phase <= #4 4'b0100; end endmodule
module Step_Count (clk_5x, phase); input clk_5x; output [2:0] phase; reg [2:0] phase; always@(posedge clk_5x) case (phase) 0:phase = #1 1; 1:phase = #1 2; 2:phase = #1 3; 3:phase = #1 4; default: phase = #1 0; endcase endmodule
module race(clk, q0); input clk, q0; reg q1, q2; always @(posedge clk) q1 = #1 q0; always @(posedge clk) q2 = #1 q1; endmodule
module no_race_1(clk, q0, q2); input clk, q0; output q2; reg q1, q2; always @(posedge clk) begin q2 = q1; q1 = q0; end endmodule
module no_race_2(clk, q0, q2); input clk, q0; output q2; reg q1, q2; always @(posedge clk) q1 <= #1 q0; always @(posedge clk) q2 <= #1 q1; endmodule
module And_Always(x, y, z); input x,y; output z; reg z; always @(x or y) z <= x & y; // combinational logic method 1 endmodule
module And_Assign(x, y, z); input x,y; output z; wire z; assign z <= x & y; // combinational logic method 2 = method 1 endmodule
module And_Or (a,b,c,z); input a,b,c; output z; reg [1:0]z; always @(a or b or c) begin z[1]<= &{a,b,c}; z[2]<= |{a,b,c}; end endmodule
module Parity (BusIn, outp); input[7:0] BusIn; output outp; reg outp; always @(BusIn) if (^Busin == 0) outp = 1; else outp = 0; endmodule
module And_Bad(a, b, c); input a, b; output c; reg c; always@(a) c <= a & b; // b is missing from this sensitivity list endmodule
module CL_good(a, b, c); input a, b; output c; reg c; always@(a or b) begin c = a + b; d = a & b; e = c + d; end // c, d: LHS before RHS endmodule module CL_bad(a, b, c); input a, b; output c; reg c; always@(a or b) begin e = c + d; c = a + b; d = a & b; end // c, d: RHS before LHS endmodule
// The complement of this function is too big for synthesis. module Achilles (out, in); output out; input [30:1] in; assign out = in[30]&in[29]&in[28] | in[27]&in[26]&in[25] | in[24]&in[23]&in[22] | in[21]&in[20]&in[19] | in[18]&in[17]&in[16] | in[15]&in[14]&in[13] | in[12]&in[11]&in[10] | in[9] & in[8]&in[7] | in[6] & in[5]&in[4] | in[3] & in[2]&in[1]; endmodule
module Mux_21a(sel, a, b, z); input sel, a , b; output z; reg z; always @(a or b or sel) begin case(sel) 1'b0: z <= a; 1'b1: z <= b; end endmodule
module Mux_x(sel, a, b, z); input sel, a, b; output z; reg z; always @(a or b or sel) begin case(sel) 1'b0: z <= 0; 1'b1: z <= 1; 1'bx: z <= 'x'; end endmodule
module Mux_21b(sel, a, b, z); input sel, a, b; output z; reg z; always @(a or b or sel) begin if (sel) z <= a else z <= b; end endmodule
module Mux_Latch(sel, a, b, z); input sel, a, b; output z; reg z; always @(a or sel) begin if (sel) z <= a; end endmodule
module Mux_81(InBus, sel, OE, OutBit); input [7:0] InBus; input [2:0] Sel; input OE; output OutBit; reg OutBit; always @(OE or sel or InBus) begin if (OE == 1) OutBit = InBus[sel]; else OutBit = 1'bz; end endmodule
module case8_oneHot(oneHot, a, b, c, z); input a, b, c; input [2:0] oneHot; output z; reg z; always @(oneHot or a or b or c) begin case(oneHot) //synopsys full_case 3'b001: z <= a; 3'b010: z <= b; 3'b100: z <= c; default: z <= 1'bx; endcase end endmodule
module case8_priority(oneHot, a, b, c, z); input a, b, c; input [2:0] oneHot; output z; reg z; always @(oneHot or a or b or c) begin case(1'b1) //synopsys parallel_case oneHot[0]: z <= a; oneHot[1]: z <= b; oneHot[2]: z <= c; default: z <= 1'bx; endcase end endmodule
module Decoder_4To16(enable, In_4, Out_16); // 4-to-16 decoder input enable; input [3:0] In_4; output [15:0] Out_16; reg [15:0] Out_16; always @(enable or In_4) begin Out_16 = 16'hzzzz; if (enable == 1) begin Out_16 = 16'h0000; Out_16[In_4] = 1; end end endmodule
module Pri_Encoder32 (InBus, Clk, OE, OutBus); input [31:0]InBus; input OE, Clk; output [4:0]OutBus; reg j; reg [4:0]OutBus; always@(posedge Clk) begin if (OE == 0) OutBus = 5'bz ; else begin OutBus = 0; for (j = 31; j >= 0; j = j - 1) begin if (InBus[j] == 1) OutBus = j; end end end endmodule
module Adder_8 (A, B, Z, Cin, Cout); input [7:0] A, B; input Cin; output [7:0] Z; output Cout; assign {Cout, Z} = A + B + Cin; endmodule
module Adder_16 (A, B, Sum, Cout); input [15:0] A, B; output [15:0] Sum; output Cout; reg [15:0] Sum; reg Cout; always @(A or B) {Cout, Sum} = A + B + 1; endmodule
module Add_A (sel, a, b, c, d, y); input a, b, c, d, sel; output y; reg y; always@(sel or a or b or c or d) begin if (sel == 0) y <= a + b; else y <= c + d; end endmodule
module Add_B (sel, a, b, c, d, y); input a, b, c, d, sel; output y; reg t1, t2, y; always@(sel or a or b or c or d) begin if (sel == 0) begin t1 = a; t2 = b; end // Temporary else begin t1 = c; t2 = d; end // variables. y = t1 + t2; end endmodule
module Multiply_unsigned (A, B, Z); input [1:0] A, B; output [3:0] Z; assign Z <= A * B; endmodule
module Multiply_signed (A, B, Z); input [1:0] A, B; output [3:0] Z; // 00 -> 00_00 01 -> 00_01 10 -> 11_10 11 -> 11_11 assign Z = { { 2{A[1]} }, A} * { { 2{B[1]} }, B}; endmodule
module Counter_With_Reset (count, clock, reset); input clock, reset; output count; reg [7:0] count; always @ (posedge clock or negedge reset) if (reset == 0) count = 0; else count = count + 1; endmodule
module DFF_MasterSlave (D, clock, reset, Q); // D type flip-flop input D, clock, reset; output Q; reg Q, latch; always @(posedge clock or posedge reset) if (reset == 1) latch = 0; else latch = D; // the master. always @(latch) Q = latch; // the slave. endmodule
module Count4(clk, reset, Q0, Q1, Q2, Q3); input clk, reset; output Q0, Q1, Q2, Q3; wire Q0, Q1, Q2, Q3; // Q , D , clk, reset asDff dff0( Q0, ~Q0, clk, reset); // The asDff is a asDff dff1( Q1, ~Q1, Q0, reset); // standard component, asDff dff2( Q2, ~Q2, Q1, reset); // unique to one set of tools. asDff dff3( Q3, ~Q3, Q2, reset); endmodule
module asDff (D, Q, Clk, Rst); parameter width = 1, reset_value = 0; input [width-1:0] D; output [width-1:0] Q; reg [width-1:0] Q; input Clk,Rst; initial Q = {width{1'bx}}; always @ ( posedge Clk or negedge Rst ) if ( Rst==0 ) Q <= #1 reset_value; else Q <= #1 D; endmodule
module DP_csum(A1,B1,Z1); input [3:0] A1,B1; output Z1; reg [3:0] Z1; always@(A1 or B1) Z1 <= A1 + B1;//Compass adder_arch cond_sum_add endmodule
module DP_ripp(A2,B2,Z2); input [3:0] A2,B2; output Z2; reg [3:0] Z2; always@(A2 or B2) Z2 <= A2 + B2;//Compass adder_arch ripple_add endmodule
module DP_sub_A(A,B,OutBus,CarryIn); input [3:0] A, B ; input CarryIn ; output OutBus ; reg [3:0] OutBus ; always@(A or B or CarryIn) OutBus <= A - B - CarryIn ; endmodule
module DP_sub_B (A, B, CarryIn, Z) ; input [3:0] A, B, CarryIn ; output [3:0] Z; reg [3:0] Z; always@(A or B or CarryIn) begin case (CarryIn) 1'b1 : Z <= A - B - 1'b1; default : Z <= A - B - 1'b0; endcase end endmodule
entity And_Bad is port (a, b: in BIT; c: out BIT); end And_Bad; architecture Synthesis_Bad of And_Bad is begin process (a) -- this should be process (a, b) begin c <= a and b; end process; end Synthesis_Bad;
entity Mux4 is port (i: BIT_VECTOR(3 downto 0); sel: BIT_VECTOR(1 downto 0); s: out BIT); end Mux4; architecture Synthesis_1 of Mux4 is begin process(sel, i) begin case sel is when "00" => s <= i(0); when "01" => s <= i(1); when "10" => s <= i(2); when "11" => s <= i(3); end case; end process; end Synthesis_1;
architecture Synthesis_2 of Mux4 is begin with sel select s <= i(0) when "00", i(1) when "01", i(2) when "10", i(3) when "11"; end Synthesis_2;
library IEEE; use ieee.std_logic_1164.all; entity Mux8 is port (InBus : in STD_LOGIC_VECTOR(7 downto 0); Sel : in INTEGER range 0 to 7; OutBit : out STD_LOGIC); end Mux8; architecture Synthesis_1 of Mux8 is begin process(InBus, Sel) variable TmpBus : STD_LOGIC_VECTOR (7 downto 0); begin OutBit <= InBus(Sel); end process; end Synthesis_1;
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity Decoder is port (enable : in BIT; Din: STD_LOGIC_VECTOR (2 downto 0); Dout: out STD_LOGIC_VECTOR (7 downto 0)); end Decoder; architecture Synthesis_1 of Decoder is begin with enable select Dout <= STD_LOGIC_VECTOR (UNSIGNED' (shift_left ("00000001", TO_INTEGER (UNSIGNED(Din)) ) ) ) when '1', "11111111" when '0', "00000000" when others; end Synthesis_1;
library IEEE; use IEEE.NUMERIC_STD.all; use IEEE.STD_LOGIC_1164.all; entity Concurrent_Decoder is port ( enable : in BIT; Din : in STD_LOGIC_VECTOR (2 downto 0); Dout : out STD_LOGIC_VECTOR (7 downto 0)); end Concurrent_Decoder; architecture Synthesis_1 of Concurrent_Decoder is begin process (Din, enable) variable T : STD_LOGIC_VECTOR(7 downto 0); begin if (enable = '1') then T := "00000000"; T( TO_INTEGER (UNSIGNED(Din))) := '1'; Dout <= T ; else Dout <= (others => 'Z'); end if; end process; end Synthesis_1;
library IEEE; use IEEE.NUMERIC_STD.all; use IEEE.STD_LOGIC_1164.all; entity Adder_1 is port (A, B: in UNSIGNED(3 downto 0); C: out UNSIGNED(4 downto 0)); end Adder_1; architecture Synthesis_1 of Adder_1 is begin C <= ('0' & A) + ('0' & B); end Synthesis_1;
library IEEE; use IEEE.STD_LOGIC_1164.all; entity DFF_With_Reset is port(D, Clk, Reset : in STD_LOGIC; Q : out STD_LOGIC); end DFF_With_Reset; architecture Synthesis_1 of DFF_With_Reset is begin process(Clk, Reset) begin if (Reset = '0') then Q <= '0'; -- asynchronous reset elsif rising_edge(Clk) then Q <= D; end if; end process; end Synthesis_1; architecture Synthesis_2 of DFF_With_Reset is begin process begin wait until rising_edge(Clk); -- This reset is gated with the clock and is synchronous: if (Reset = '0') then Q <= '0'; else Q <= D; end if; end process; end Synthesis_2;
`timescale 1ns/1ns module halfgate (myInput, myOutput); input myInput; output myOutput; wire myOutput; assign myOutput = ~myInput; endmodule
library IEEE; use IEEE.STD_LOGIC_1164.all; library COMPASS_LIB; use COMPASS_LIB.COMPASS.all; --compass compile_off -- synopsys etc. use COMPASS_LIB.COMPASS_ETC.all; --compass compile_on -- synopsys etc. entity halfgate_u is --compass compile_off -- synopsys etc. generic ( myOutput_cap : Real := 0.01; INSTANCE_NAME : string := "halfgate_u" ); --compass compile_on -- synopsys etc. port ( myInput : in Std_Logic := 'U'; myOutput : out Std_Logic := 'U' ); end halfgate_u; architecture halfgate_u of halfgate_u is component in01d0 port ( I : in Std_Logic; ZN : out Std_Logic ); end component; begin u2: in01d0 port map ( I => myInput, ZN => myOutput ); end halfgate_u; --compass compile_off -- synopsys etc. library cb60hd230d; configuration halfgate_u_CON of halfgate_u is for halfgate_u for u2 : in01d0 use configuration cb60hd230d.in01d0_CON generic map ( ZN_cap => 0.0100 + myOutput_cap, INSTANCE_NAME => INSTANCE_NAME&"/u2" ) port map ( I => I, ZN => ZN); end for; end for; end halfgate_u_CON; --compass compile_on -- synopsys etc.
component ASDFF generic (WIDTH : POSITIVE := 1; RESET_VALUE : STD_LOGIC_VECTOR := "0" ); port (Q : out STD_LOGIC_VECTOR (WIDTH-1 downto 0); D : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); CLK : in STD_LOGIC; RST : in STD_LOGIC ); end component;
library IEEE, COMPASS_LIB; use IEEE.STD_LOGIC_1164.all; use COMPASS_LIB.STDCOMP.all; entity Ripple_4 is port (Trig, Reset: STD_LOGIC; QN0_5x: out STD_LOGIC; Q : inout STD_LOGIC_VECTOR(0 to 3)); end Ripple_4; architecture structure of Ripple_4 is signal QN : STD_LOGIC_VECTOR(0 to 3); component in01d1 port ( I : in Std_Logic; ZN : out Std_Logic ); end component; component in01d5 port ( I : in Std_Logic; ZN : out Std_Logic ); end component; begin --compass dontTouch inv5x -- synopsys dont_touch etc. -- Named association for hand-instantiated library cells: inv5x: IN01D5 port map( I=>Q(0), ZN=>QN0_5x ); inv0 : IN01D1 port map( I=>Q(0), ZN=>QN(0) ); inv1 : IN01D1 port map( I=>Q(1), ZN=>QN(1) ); inv2 : IN01D1 port map( I=>Q(2), ZN=>QN(2) ); inv3 : IN01D1 port map( I=>Q(3), ZN=>QN(3) ); -- Positional association for standard components: -- Q D Clk Rst d0: asDFF port map(Q (0 to 0), QN(0 to 0), Trig, Reset); d1: asDFF port map(Q (1 to 1), QN(1 to 1), Q(0), Reset); d2: asDFF port map(Q (2 to 2), QN(2 to 2), Q(1), Reset); d3: asDFF port map(Q (3 to 3), QN(3 to 3), Q(2), Reset); end structure;
`timescale 1ns / 10ps module ripple_4_u (trig, reset, qn0_5x, q); input trig; input reset; output qn0_5x; inout [3:0] q; wire [3:0] qn; supply1 VDD; supply0 VSS; in01d5 inv5x (.I(q[0]),.ZN(qn0_5x)); in01d1 inv0 (.I(q[0]),.ZN(qn[0])); in01d1 inv1 (.I(q[1]),.ZN(qn[1])); in01d1 inv2 (.I(q[2]),.ZN(qn[2])); in01d1 inv3 (.I(q[3]),.ZN(qn[3])); dfctnb d0(.D(qn[0]),.CP(trig),.CDN(reset),.Q(q[0]),.QN(\d0.QN )); dfctnb d1(.D(qn[1]),.CP(q[0]),.CDN(reset),.Q(q[1]),.QN(\d1.QN )); dfctnb d2(.D(qn[2]),.CP(q[1]),.CDN(reset),.Q(q[2]),.QN(\d2.QN )); dfctnb d3(.D(qn[3]),.CP(q[2]),.CDN(reset),.Q(q[3]),.QN(\d3.QN )); endmodule
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity SIPO_1 is port ( Clk : in STD_LOGIC; SI : in STD_LOGIC; -- serial in PO : buffer STD_LOGIC_VECTOR(3 downto 0)); -- parallel out end SIPO_1; architecture Synthesis_1 of SIPO_1 is begin process (Clk) begin if (Clk = '1') then PO <= SI & PO(3 downto 1); end if; end process; end Synthesis_1;
module sipo_1_u (clk, si, po); input clk; input si; output [3:0] po; supply1 VDD; supply0 VSS; dfntnb po_ff_b0 (.D(po[1]),.CP(clk),.Q(po[0]),.QN(\po_ff_b0.QN)); dfntnb po_ff_b1 (.D(po[2]),.CP(clk),.Q(po[1]),.QN(\po_ff_b1.QN)); dfntnb po_ff_b2 (.D(po[3]),.CP(clk),.Q(po[2]),.QN(\po_ff_b2.QN)); dfntnb po_ff_b3 (.D(si),.CP(clk),.Q(po[3]),.QN(\po_ff_b3.QN )); endmodule
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity SIPO_R is port ( clk : in STD_LOGIC ; res : in STD_LOGIC ; SI : in STD_LOGIC ; PO : out STD_LOGIC_VECTOR(3 downto 0)); end; architecture Synthesis_1 of SIPO_R is signal PO_t : STD_LOGIC_VECTOR(3 downto 0); begin process (PO_t) begin PO <= PO_t; end process; process (clk, res) begin if (res = '0') then PO_t <= (others => '0'); elsif (rising_edge(clk)) then PO_t <= SI & PO_t(3 downto 1); end if; end process; end Synthesis_1;
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity Adder4 is port ( in1, in2 : in BIT_VECTOR(3 downto 0) ; mySum : out BIT_VECTOR(3 downto 0) ) ; end Adder4; architecture Behave_A of Adder4 is function DIY(L,R: BIT_VECTOR(3 downto 0)) return BIT_VECTOR is variable sum:BIT_VECTOR(3 downto 0);variable lt,rt,st,cry: BIT; begin cry := '0'; for i in L'REVERSE_RANGE loop lt := L(i); rt := R(i); st := lt xor rt; sum(i):= st xor cry; cry:= (lt and rt) or (st and cry); end loop; return sum; end; begin mySum <= DIY (in1, in2); -- do it yourself (DIY) add end Behave_A;
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity Adder4 is port ( in1, in2 : in UNSIGNED(3 downto 0) ; mySum : out UNSIGNED(3 downto 0) ) ; end Adder4; architecture Behave_B of Adder4 is begin mySum <= in1 + in2; -- This uses an overloaded '+'. end Behave_B;
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity Adder_Subtracter is port ( xin : in UNSIGNED(15 downto 0); clk, addsub, clr: in STD_LOGIC; result : out UNSIGNED(15 downto 0)); end Adder_Subtracter; architecture Behave_A of Adder_Subtracter is signal addout, result_t: UNSIGNED(15 downto 0); begin result <= result_t; with addsub select addout <= (xin + result_t) when '1', (xin - result_t) when '0', (others => '-') when others; process (clr, clk) begin if (clr = '0') then result_t <= (others => '0'); elsif rising_edge(clk) then result_t <= addout; end if; end process; end Behave_A;
architecture Behave_B of Adder_Subtracter is signal result_t: UNSIGNED(15 downto 0); begin result <= result_t; process (clr, clk) begin if (clr = '0') then result_t <= (others => '0'); elsif rising_edge(clk) then case addsub is when '1' => result_t <= (xin + result_t); when '0' => result_t <= (xin - result_t); when others => result_t <= (others => '-'); end case; end if; end process; end Behave_B;
`define resSt 0 `define S1 1 `define S2 2 `define S3 3 module StateMachine_1 (reset, clk, yOutReg); input reset, clk; output yOutReg; reg yOutReg, yOut; reg [1:0] curSt, nextSt; always @(posedge clk or posedge reset) begin:Seq //Compass statemachine oneHot curSt if (reset == 1) begin yOut = 0; yOutReg = yOut; curSt = `resSt; end else begin case (curSt) `resSt:yOut = 0;`S1:yOut = 1;`S2:yOut = 1;`S3:yOut = 1; default:yOut = 0; endcase yOutReg = yOut; curSt = nextSt; // ... update the state. end end always @(curSt or yOut) // Assign the next state: begin:Comb case (curSt) `resSt:nextSt = `S3; `S1:nextSt = `S2; `S2:nextSt = `S1; `S3:nextSt = `S1; default:nextSt = `resSt; endcase end endmodule
module StateMachine_2 (reset, clk, yOutReg); input reset, clk; output yOutReg; reg yOutReg, yOut; parameter [1:0] //synopsys enum states resSt = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11; reg [1:0] /* synopsys enum states */ curSt, nextSt; //synopsys state_vector curSt always @(posedge clk or posedge reset) begin if (reset == 1) begin yOut = 0; yOutReg = yOut; curSt = resSt; end else begin case (curSt) resSt:yOut = 0;S1:yOut = 1;S2:yOut = 1;S3:yOut = 1; default:yOut = 0; endcase yOutReg = yOut; curSt = nextSt; end end always @(curSt or yOut) begin case (curSt) resSt:nextSt = S3; S1:nextSt = S2; S2:nextSt = S1; S3:nextSt = S1; default:nextSt = S1; endcase end endmodule
library IEEE; use IEEE.STD_LOGIC_1164.all; entity SM1 is port (aIn, clk : in Std_logic; yOut: out Std_logic); end SM1; architecture Moore of SM1 is type state is (s1, s2, s3, s4); signal pS, nS : state; begin process (aIn, pS) begin case pS is when s1 => yOut <= '0'; nS <= s4; when s2 => yOut <= '1'; nS <= s3; when s3 => yOut <= '1'; nS <= s1; when s4 => yOut <= '1'; nS <= s2; end case; end process; process begin -- synopsys etc. --compass Statemachine adj pS wait until clk = '1'; pS <= nS; end process; end Moore;
dfntnb sm_ps4(.D(sm_ps1_Q),.CP(clk),.Q(sm_ps4_Q),.QN(sm_ps4_QN)); dfntnb sm_ps3(.D(sm_ps2_Q),.CP(clk),.Q(sm_ps3_Q),.QN(sm_ps3_QN)); dfntnb sm_ps2(.D(sm_ps4_Q),.CP(clk),.Q(sm_ps2_Q),.QN(sm_ps2_QN)); dfntnb sm_ps1(.D(sm_ps3_Q),.CP(clk),.Q(sm_ps1_Q),.QN(\sm_ps1.QN )); nd03d0 i_6(.A1(sm_ps4_QN),.A2(sm_ps3_QN),.A3(sm_ps2_QN), .ZN(yout_smo));
dfntnb sm_ps2(.D(i_4_ZN),.CP(clk), .Q(\sm_ps2.Q ),.QN(sm_ps2_QN)); dfntnb sm_ps1(.D(sm_ps1_QN),.CP(clk),.Q(\sm_ps1.Q ),.QN(sm_ps1_QN)); oa04d1 i_4(.A1(sm_ps1_QN),.A2(sm_ps2_QN),.B(yout_smo),.ZN(i_4_ZN)); nd02d0 i_5(.A1(sm_ps2_QN), .A2(sm_ps1_QN), .ZN(yout_smo));
dfntnb sm_ps3(.D(i_6_ZN),.CP(clk),.Q(yout_smo),.QN(sm_ps3_QN)); dfntnb sm_ps2(.D(sm_ps3_QN),.CP(clk),.Q(sm_ps2_Q),.QN(\sm_ps2.QN )); dfntnb sm_ps1(.D(i_5_ZN),.CP(clk),.Q(sm_ps1_Q),.QN(\sm_ps1.QN )); nr02d0 i_5(.A1(sm_ps3_QN),.A2(sm_ps2_Q),.ZN(i_5_ZN)); nd02d0 i_6(.A1(sm_ps1_Q),.A2(yout_smo),.ZN(i_6_ZN));
library IEEE; use IEEE.STD_LOGIC_1164.all; entity SM2 is port (aIn, clk : in Std_logic; yOut: out Std_logic); end SM2; architecture Mealy of SM2 is type state is (s1, s2, s3, s4); signal pS, nS : state; begin process(aIn, pS) begin case pS is when s1 => if (aIn = '1') then yOut <= '0'; nS <= s4; else yOut <= '1'; nS <= s3; end if; when s2 => yOut <= '1'; nS <= s3; when s3 => yOut <= '1'; nS <= s1; when s4 => if (aIn = '1') then yOut <= '1'; nS <= s2; else yOut <= '0'; nS <= s1; end if; end case; end process; process begin wait until clk = '1' ; --Compass Statemachine oneHot pS pS <= nS; end process; end Mealy;
module RAM_1(A, CEB, WEB, OEB, INN, OUTT); input [6:0] A; input CEB,WEB,OEB; input [4:0]INN; output [4:0] OUTT; reg [4:0] OUTT; reg [4:0] int_bus; reg [4:0] memory [127:0]; always@(negedge CEB) begin if (CEB == 0) begin if (WEB == 1) int_bus = memory[A]; else if (WEB == 0) begin memory[A] = INN; int_bus = INN; end else int_bus = 5'bxxxxx; end end always@(OEB or int_bus) begin case (OEB) 0 : OUTT = int_bus; default : OUTT = 5'bzzzzz; endcase end endmodule
library IEEE; use IEEE.STD_LOGIC_1164.all; package RAM_package is constant numOut : INTEGER := 8; constant wordDepth: INTEGER := 8; constant numAddr : INTEGER := 3; subtype MEMV is STD_LOGIC_VECTOR(numOut-1 downto 0); type MEM is array (wordDepth-1 downto 0) of MEMV; end RAM_package; library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use work.RAM_package.all; entity RAM_1 is port (signal A : in STD_LOGIC_VECTOR(numAddr-1 downto 0); signal CEB, WEB, OEB : in STD_LOGIC; signal INN : in MEMV; signal OUTT : out MEMV); end RAM_1; architecture Synthesis_1 of RAM_1 is signal i_bus : MEMV; -- RAM internal data latch signal mem : MEM; -- RAM data begin process begin wait until CEB = '0'; if WEB = '1' then i_bus <= mem(TO_INTEGER(UNSIGNED(A))); elsif WEB = '0' then mem(TO_INTEGER(UNSIGNED(A))) <= INN; i_bus <= INN; else i_bus <= (others => 'X'); end if; end process; process(OEB, int_bus) begin -- control output drivers: case (OEB) is when '0' => OUTT <= i_bus; when '1' => OUTT <= (others => 'Z'); when others => OUTT <= (others => 'X'); end case; end process; end Synthesis_1;
entity ShiftN is generic (TCQ:TIME := 0.3 ns; TLQ:TIME := 0.5 ns; TSQ:TIME := 0.7 ns); port( CLK, CLR, LD, SH, DIR: in BIT; D: in BIT_VECTOR(3 downto 0); Q: out BIT_VECTOR(7 downto 0) ); end ShiftN; architecture Behave of ShiftN is begin Shift: process (CLR, CLK) variable St: BIT_VECTOR(7 downto 0); begin if CLR = '1' then St := (others => '0'); Q <= St after TCQ; elsif CLK'EVENT and CLK='1' then if LD = '1' then St := (others => '0'); St(3 downto 0) := D; Q <= St after TLQ; elsif SH = '1' then case DIR is when '0'=>St:='0' & St(7 downto 1); when '1'=>St:=St(6 downto 0) & '0'; end case; Q <= St after TSQ; end if; end if; end process; end;
architecture Behave of DFFClr is signal Qi : BIT; begin QB <= not Qi; Q <= Qi; process (CLR, CLK) begin if CLR = '1' then Qi <= '0' after TRQ; elsif CLK'EVENT and CLK = '1' then Qi <= D after TCQ; end if; end process; end;
library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.NUMERIC_STD.all; entity fifo_control is generic TPD:TIME := 1 ns; port(D_1, D_2: in UNSIGNED(11 downto 0); sel : in UNSIGNED(1 downto 0) ; read , f1, f2, e1, e2 : in STD_LOGIC; r1, r2, w12:out STD_LOGIC; D: out UNSIGNED(11 downto 0); OE:out STD_LOGIC ) ; end; architecture rtl of fifo_control is begin process (read, sel, D_1, D_2, f1, f2, e1, e2) begin r1 <= '0' after TPD; r2 <= '0' after TPD; OE_b <= '0' after TPD; if (read = '1') then w12 <= '0' after TPD; case sel is when "01" => D <= D_1 after TPD; r1 <= '1' after TPD; when "10" => D <= D_2 after TPD; r2 <= '1' after TPD; when "00" => D(3) <= f1 after TPD; D(2) <= f2 after TPD; D(1) <= e1 after TPD; D(0) <= e2 after TPD; D(11 downto 4) <= "00000000" after TPD; when others => OE_b <= '1' after TPD; end case; elsif (read = '0') then OE_b <= '0' after TPD; w12 <= '1' after TPD; else OE_b <= '0' after TPD; end if; end process; end rtl;
library COMPASS_LIB, IEEE ; use IEEE.STD.all; use IEEE.NUMERIC_STD.all; use COMPASS_LIB.STDCOMP.all; use COMPASS_LIB.COMPASS.all; entity t_control_ASIC is port( PadTri : out STD_LOGIC_VECTOR (11 downto 0) ; PadClk, PadInreset, PadInreadv : in STD_LOGIC_VECTOR ( 0 downto 0) ; PadInp1, PadInp2 : in STD_LOGIC_VECTOR (11 downto 0) ; PadInSens : in STD_LOGIC_VECTOR ( 1 downto 0) ) ; end t_control_ASIC ; architecture structure of t_control_ASIC is for all : asPadIn use entity COMPASS_LIB.aspadIn(aspadIn) ; for all : asPadClk use entity COMPASS_LIB.aspadClk(aspadClk); for all : asPadTri use entity COMPASS_LIB.aspadTri(aspadTri) ; for all : asPadVdd use entity COMPASS_LIB.aspadVdd(aspadVdd) ; for all : asPadVss use entity COMPASS_LIB.aspadVss(aspadVss) ; component pc3c01 port ( cclk : in STD_LOGIC; cp : out STD_LOGIC ); end component; component t_control port(T_in1, T_in2 : in UNSIGNED(11 downto 0); SENSOR: in UNSIGNED( 1 downto 0) ; clk, rd, rst : in STD_LOGIC; D : out UNSIGNED(11 downto 0); oe_b : out STD_LOGIC ); end component ; signal T_in1_sv, T_in2_sv : STD_LOGIC_VECTOR(11 downto 0) ; signal T_in1_un, T_in2_un : UNSIGNED(11 downto 0) ; signal sensor_sv : STD_LOGIC_VECTOR(1 downto 0) ; signal sensor_un : UNSIGNED(1 downto 0) ; signal clk_sv, rd_fifo_sv, reset_sv : STD_LOGIC_VECTOR (0 downto 0) ; signal clk_core, oe_b : STD_LOGIC ; signal D_un : UNSIGNED(11 downto 0) ; signal D_sv : STD_LOGIC_VECTOR(11 downto 0) ; begin --compass dontTouch u* -- synopsys dont_touch etc. u1 : asPadIn generic map(12,"2:13") port map(t_in1_sv,PadInp1) ; u2 : asPadIn generic map(12,"14:25") port map(t_in2_sv,PadInp2) ; u3 : asPadIn generic map(2,"26:27") port map(sensor_sv, PadInSens ) ; u4 : asPadIn generic map(1,"29") port map(rd_fifo_sv, PadInReadv ) ; u5 : asPadIn generic map(1,"30") port map(reset_sv, PadInreset ) ; u6 : asPadIn generic map(1,"32") port map(clk_sv, PadClk) ; u7 : pc3c01 port map(clk_sv(0), clk_core) ; u8 : asPadTri generic map(12,"35:38,41:44,47:50") port map(PadTri,D_sv,oe_b); u9 : asPadVdd generic map("1,31,34,40,45,52") port map(Vdd) ; u10: asPadVss generic map("28,33,39,46,51,53") port map(Vss) ; T_in1_un <= UNSIGNED(T_in1_sv) ; T_in2_un <= UNSIGNED(T_in2_sv) ; sensor_un <= UNSIGNED(sensor_sv) ; D_sv <= STD_LOGIC_VECTOR(D_un) ; v_1 : t_control port map (T_in1_un,T_in2_un,sensor_un, Clk_core, rd_fifo_sv(0), reset_sv(0),D_un, oe_b) ; end;
`timescale 1ns / 10ps module comp_mux_o (a, b, outp); input [2:0] a; input [2:0] b; output [2:0] outp; supply1 VDD; supply0 VSS; mx21d1 B1_i1 (.I0(a[0]), .I1(b[0]), .S(B1_i6_ZN), .Z(outp[0])); oa03d1 B1_i2 (.A1(B1_i9_ZN), .A2(a[2]), .B1(a[0]), .B2(a[1]), .C(B1_i4_ZN), .ZN(B1_i2_ZN)); nd02d0 B1_i3 (.A1(a[1]), .A2(a[0]), .ZN(B1_i3_ZN)); nd02d0 B1_i4 (.A1(b[1]), .A2(B1_i3_ZN), .ZN(B1_i4_ZN)); mx21d1 B1_i5 (.I0(a[1]), .I1(b[1]), .S(B1_i6_ZN), .Z(outp[1])); oa04d1 B1_i6 (.A1(b[2]), .A2(B1_i7_ZN), .B(B1_i2_ZN), .ZN(B1_i6_ZN)); in01d0 B1_i7 (.I(a[2]), .ZN(B1_i7_ZN)); an02d1 B1_i8 (.A1(b[2]), .A2(a[2]), .Z(outp[2])); in01d0 B1_i9 (.I(b[2]), .ZN(B1_i9_ZN)); endmodule
.model comp_mux .inputs a0 b0 a1 b1 a2 b2 .outputs outp0 outp1 outp2 .names a0 b0 a1 b1 a2 b2 sel 100000 1 101100 1 --1000 1 ----10 1 100011 1 101111 1 --1011 1 .names sel a0 b0 outp0 1-1 1 01- 1 .names sel a1 b1 outp1 1-1 1 01- 1 .names sel a2 b2 outp2 1-1 1 01- 1 .exdc .names a0 b0 a1 b1 a2 b2 sel 000000 1 110000 1 001100 1 111100 1 000011 1 110011 1 001111 1 111111 1 .end
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