Compaction allows a high degree of freedom where most needed for DSM-technology-based layouts to take full advantage of advances in processing technology. Below are some of the critical benefits of compaction:

  1. To avoid “compacting” all layout dimensions to the minimum listed in the process file, the functionality of certain devices has to be recognizable from the layout data. This is possible with compaction. These devices can then be resized with scale factors, sized according to process-specific or electrical rule-specific criteria, or resized from and associated with text labels preserved and kept together with the features labeled. These features are critically important for such things as enhancing yield or optimizing performance.
  2. Power and ground can be identified and sized differently.
  3. Oversizing of metal widths (wide metal), tubs, and other desired features is possible.
  4. Netlist-dependent design rules are possible where the nctlist is identified from text labels and built from layer connectivity information in the process file.
  5. Two-dimensional abutment can be done automatically, based on layer matching.
  6. Within the newly achieved reduced area of the migrated block, the local geometries can be optimized according to area-, capacitance- and resistance-related cost factors.
  7. All polygon edges and particularly contacts (pins) will be placed on a grid to make abutment and area-based router interconnections possible.
  8. If there are conflicts in the layout so that certain layout features do not fit in the available space, graphical feedback will guide the user to eliminate these conflicts. These kinds of conflicts can also be eliminated automatically by the system if specified by the user.

Figure 2.2 indicates some of the great flexibility in resizing gate lengths for a group of transistors, the gate length of an individual transistor and supply and clock nets, all independently. Upper part is premigration; lower part is postmigration.

Fig. 2.2 Flexibility in Resizing Features With Compaction


It should be obvious thai linear shrink and even “creative” linear shrink will run out of steam as DSM advances. Migrating layouts to technologies with increasingly smaller minimum dimensions can not possibly mean just linearly scaling all dimensions. Clearly, process improvements do not follow a linear scale.

If we consider taking a process from, for example, a 0.28 micron process to a 0.18 micron process, only certain minimum dimensions change from 0.28 microns to 0.18 microns. One of these is generally the minimum transistor gate length dimension, the gate dimension that dominates the electrical characteristics of the channel between a MOS transistor source and drain. For reasons of sanity (or to avoid discussion that will most certainly border on insanity), we assume that every manufacturer advertising these minimal dimensions means the same thing.

So, while the gate dimensions for the two 0.18 micron processes are the same, many of the other minimally allowed layout dimensions are probably not. Therefore, a chip migrated to 0.18 micron processes of two different foundries will have different layout densities, different sizes and different power and speed performances. This is because a comparison of 0.18 micron processes, for instance, from different vendors will reveal significant differences in the various sets of process rules. As a result, migration to the different 0.18 micron processes of different foundries will yield blocks of different overall dimensions and different performance parameters for one and the same original (source) layout.

Because of the very great influence of layout geometries on chip behavior, we must be able to adjust each and every layout dimension on the chip to the most appropriate value, based on criteria such as speed, power, signal integrity, etc. We can not tolerate the typical behavior in a linear shrink for the process of reduction, when just any one of the layout dimensions on the chip reaches the minimum despite how oversized all other layout dimensions may be. Figure 2.3 gives a simple illustration of how the results of a shrink differ from compaction. A to B shows a change of every layout dimension, according to a common shrink factor. B to C shows the reduction of the overall dimensions of the cell, using compaction, without any change in the dimensions of the device or supply lines. The difference here is not great, but the benefits add up for an entire chip.

As we proceed, the benefits of compaction versus shrink will gradually become more convincing. Chapter 3 on layout manipulations for optimization will particularly add a lot to the arsenal of pro-compaction arguments.

Fig. 2.3 There is Shrink, and Then There is Compaction