Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002 Donnamaie E. White


Design Optimization

Last Edit July 22, 2001

Optimization Approaches

There are several approaches to optimizing a design as shown in Table 4-1.

Table 4-1 Design Optimization Objectives

General Design Optimization Objectives
  • improve speed and minimize distortion
  • balance speed (tracking)
  • reduce internal cell utilization
  • reduce I/O pin count
  • reduce power
  • (lower the junction temperature)
  • increase circuit testability
  • increase circuit reliability
  • reduce cost

These "design objectives" are often incompatible. Each design will have its own priority order for these items, establishing the basis for decisions where choices must be made.

For example, design requirements may include a power dissipation limit or a junction temperature restriction. Solving the power equation may violate the speed requirements.

The maximum specified operating frequency and critical path performance are usually clearly defined. Balanced path design is essential in communications circuits and has its own restrictions and tracking requirements. Macros selected to allow speed to be achieved may increase power while macros chosen to allow balanced delays may increase cell utilization.

Cell utilization can determine which array in a series is acceptable, and the larger arrays do cost more. Cell reduction techniques may affect final speed, power and cost.

The reliability of the circuit is a question of the "trickiness" of the timing and the logic design. The so-called "hot dog" designers are as welcome in a company as their software counterparts - their designs are difficult to build, test or maintain. Modular designs are an important reliability and testability issue. Modularity may require additional macros for degating while testability may require additional macros for test point monitoring or circuits such as scan-path.

A circuit must be testable to at least the 90% confidence level, preferably higher, and testability issues should have been in place before the design start. Refinements to the circuit testability are what should be required at this point in the design cycle.

Circuits with design for test (DFT) modules will average 10-20% more cells than circuits that do not use DFT. DFT circuits are easier to develop test vectors for than non-DFT circuits and they require significantly less vectors. (See Chapter 8.)

The size of the test vector set also has an effect on cost. It is more costly to develop a large set of vectors, more time consuming to fault-grade them and takes more tester time to test the die.


There are several basic design approaches that can help the designer achieve the desired speed from the circuit. A list is provided in Table 4-2.

Table 4-2 Designing For A High-Speed Circuit

Design Procedures for a High-Speed Circuit

  • Minimize the circuit logic.
  • Evaluate several implementations of speed-critical paths.
  • Reduce interconnections, gate count and chip area.
  • Use dense, silicon-efficient macros where possible.
  • Use the correct macro-option or version.
  • Place signals efficiently in multilevel gating structures. Place late-arriving signals as last-level inputs.
  • Place critical signals on the fastest paths when the macro has more than one propagation delay.
  • Where there are complementary outputs on a macro, alternate the signal to balance loading delays, watching loads, drive-factors.
  • Where there are complementary outputs, use the fastest path to propagate a critical signal.
  • Duplicate logic to reduce the fan-out and metal load delay in the critical path (balance this against the added load delay to duplicate the signal and added silicon).
  • Use the correct-drive macro for the fan-out at each net (do not overload). Do not use high fan-out drivers for low loads. Use fan-out derating on all macros except identified super-drivers.
  • Avoid wire-ORs when available as they add to metal loading.
  • Use binary counters instead of shift counters (parallel versus serial).
  • Use parallel load counters and parallel data transfer.
  • Use carry-look ahead, carry generate-propagate and other fast-adder techniques
  • Choose the design for high-input logic gates carefully. Investigate design options and their speeds.
  • Perform a pulse-distortion review and minimize distortion in critical paths.
  • Minimize output pin capacitive loading, both system load and package pin capacitance.
  • Last resort: specify placement restrictions for difficult paths (less than 20% of the paths in the array).
  • Last resort: ask the vendor for a custom macro to enhance speed.



Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com

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