Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002 Donnamaie E. White

 

Simulation

Last Edit July 22, 2001


Parametric Simulation

Since there is a gate tree, a parametric vector set can be easily constructed using the Minimal Test Sequence. The sequence requires that only one input change per vector, that each input toggle in both directions and that the output (PARAM) toggles with each vector.

Figure 8-3 shows a parametric vector file for a 32-bit version of the register. Sampling and format are vendor-specific, and the 100 ns step was used. Note that the reset is executed at the beginning as it was for the functional vectors. This will produce an error message during parametric vector checking.

Figure 8-3 Parametric Simulation - 32-Bit Register (partial)

Figure 8-3b Parametric Simulation - 32-Bit Register - Full Listing

By combining the functional and parametric vectors, 100% fault coverage is obtained for a circuit. Only sampled simulations are submitted.

Exercise

Create a complete parametric vector set for the schematics shown in the
Appendix of Chapter 3.

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com

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