Hard IP, an introduction
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For the purpose of reliability and other reasons, electrical contacts in VLSI designs are often made of multiple contacts as opposed to the big one shown in Figure 2.11 in the rectangle at the far left. Either of the two contact geometries can be chosen by the user. If, however, a multiple contacts structure is desired, a lot of work can be saved if it is done automatically with compaction, while at the same time only the number of contacts is implemented that still fits the dimensions of the new technology. This is shown from left to right in Figure 2.10.

Fig. 2.10 Automatic Recontacting: A Labor Saving Feature


Visualizing compaction in the x-coordinate direction for the moment, polygon compaction “pulls” all the vertical polygons as closely towards x=0 (to the left) in the coordinate system as the process and the electrical design rules allow (compaction in the y-coordinates would pull horizontal edges towards y=0). The result of this is illustrated in the center rectangle in Figure 2.11. For many reasons this is undesirable. The migrated layout should closely resemble the original layout.

Fig. 2.11 Maintaining Relative Positioning Through Migration

We need to optimize layout for it to approach the geometric relationships of the source layout. After all, we know that the relationships, the proportions between the layout geometries of the original layout led to a workable design. Very similar proportions can be achieved in the migrated layout by asking the compactor to optimize the new layout so that it resembles the old one while maintaining the newly achieved layout area. This process is called wire length or area optimization and is done automatically as part of the compaction process.

Fig. 2.12 Trade-offs in Layout Through Weighting Functions

There is more that can be done with area optimization than just maintaining the basic geometric proportions as they were in the premigrated layout. In Figure 2.12, we see a structure where we have a choice over a given length between using metal or a diffusion. Using cost factors (sometimes referred to as weighting functions) during area optimization, the compactor can trade One material for another. Over its length, we can adjust the structure's resistance, Of course, other structures with other trade-off parameters could be created. Designers of VLSI circuits sometimes place these types of structures to minimize rework in case a chip does not meet intended performance parameters.

In Figure 2.12, the left hand structure is achieved by assigning a large cost factor to the metal. The structure has maximum resistance, while the right structure has minimum resistance This process can be achieved through area optimization.

The results in Figure 2.1 1 were achieved by keeping the same cost factors as the premigration layout.

The results in Figure 2.12 were achieved by “playing” with different cost factors.

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