SANTA CLARA, Calif., – July 31, 2012 – Calypto® Design Systems, Inc., a leader in SOC design and optimization, today announced record results for the 49th Design Automation Conference (DAC). Calypto attributes its DAC success to the recent launch of Catapult® Low-Power High-Level Synthesis (HLS), the first HLS tool to include power as a top level design constraint, and the #1 ranking of their PowerPro product family for RTL power reduction on John Cooley’s ‘Must See List for DAC 2012’ on DeepChip.com.
Calypto DAC Booth Traffic Up
Over the three-day conference, Calypto saw a 2x increase in unique visitors and a 46% increase in suite attendees. Part of Calypto’s DAC success can be attributed to being tied for #1 in the ‘must see’ product category on John Cooley’s annual Cheesy Must See at DAC list.
“It’s clear from what my readers are saying that optimizing chip power at the gate level is too late in the design flow,” said John Cooley of DeepChip.com. “It's only at the RTL stage where you can make the big tradeoffs needed to get significant power savings.”
Calypto’s PowerPro product leverages its patented sequential analysis technology to reduce power across all sections of today’s challenging SOC designs. Supporting both fully automatic and manual use modes, PowerPro performs complex RTL clock gating and memory gating optimizations that previously could only be done manually. When compared to a traditional manual effort, PowerPro’s customers routinely achieve greater power reduction in a fraction of the time. In addition, Calypto announced at DAC that RTL power analysis has been added to PowerPro. Also based on sequential analysis, this unique capability combines the performance of RTL analysis with the accuracy of gate-level analysis. Initial results show power analysis accuracy within 15% of gate-level techniques while maintaining a 10x speed improvement.
“PowerPro is a tool at the right place at the right time, with RTL power reduction being such a hot topic for chip designers this year,” added Cooley.
Calypto Catapult LP
The other major announcement at DAC was Calypto’s launch of Catapult LP, the industry's first production quality HLS tool to add power as an optimization goal. By integrating Calypto’s existing best in class PowerPro engine “under the hood”, Catapult LP provides the industry’s first HLS tool to optimize designs for power at the architecture level, where 80% of power decisions are made. By optimizing for power, performance, and area simultaneously, users can create the most efficient designs possible.
“It’s clear that engineers are taking notice of Calypto’s unique ability to optimize across the entire SoC,” said Shawn McCloud, Vice President of Marketing at Calypto. “We saw strong growth in all three products including PowerPro for RTL power reduction, Catapult for SystemC/C++ synthesis and SLEC for formal verification across models with sequential differences.”
About Calypto’s Products
Catapult high-level synthesis, SLEC® (Sequential Logic Equivalence Checking), and PowerPro platforms are used to design, verify and optimize complex SoC and FPGA designs by seven out of the top ten semiconductor companies and over 100 leading consumer electronics companies worldwide. Calypto’s products enable engineers to dramatically improve design quality and reduce power consumption of their SoC while significantly reducing overall design and verification time.
Calypto Design Systems, Inc. is the leader in ESL hardware design and RTL power optimization.
Calypto, whose customers include Fortune 500 companies worldwide, is a member of the ARM Connected Community, Cadence Connections program, the IEEE‐SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2 and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America.
More information can be found at www.calypto.com.
DeepChip.com is a 21-year old clearinghouse where chip designers contribute first-hand evaluations and benchmarks of commercial EDA tools. The DeepChip mailing list has 31,586 subscribers and it's widely read to get an uncensored view what chip designers really think about current EDA tools. John Cooley has been doing his DAC Trip Reports and his DAC Cheesy Must See List since 1994.
Georgia Marszalek, ValleyPR, LLC for Calypto, +1-650.345.7477, Email Contact
ESL: Electronic System Level
RTL: Register Transfer Level
SoC: System on Chip
Calypto, Catapult, SLEC and PowerPro are trademarks of Calypto Design Systems Inc. DeepChip is a trademark of John Cooley. All other trademarks are property of their respective owners.