Calypto Launches Webinar Series on High Level Synthesis and RTL Power Optimization

SAN JOSE, Calif., – November 29, 2012 –  Calypto Design Systems, Inc., the leader in electronic system level (ESL) hardware design and register transfer level (RTL) power optimization, is launching a series of monthly webinars aimed at educating the design community on the latest in high level synthesis (HLS) and power optimization techniques for RTL-based designs. 

The first two webinars are “Minimizing RTL Power through Sequential Analysis”, held Tuesday, December 4 at

11:00 AM PST, and A Practical Comparison Between C++ and SystemC for High Level Synthesis”, on Thursday, December 13 at 11:00 AM PST. Due to the timeliness of the topics and the “true” technical tutorial content of the webinars, signups have been brisk with the current registration for each webinar nearing the maximum capacity of 150.

To attend these webinars, sign up at www.calypto.com/en/events.

To receive announcements of future webinars, sign up for our E-Newsletter at www.calypto.com.

About Calypto Products
Calypto’s  Catapult® High Level Synthesis,  SLEC® (Sequential Logic Equivalence Checking), and  PowerPro® platforms are used by seven out of the top ten semiconductor companies and over 100 leading consumer electronics companies worldwide. Calypto’s products enable electronic system level design to dramatically improve design quality and reduce power consumption of their system-on-chip (SoC) devices. 

About Calypto
Calypto Design Systems, Inc. is the leader in ESL hardware design and RTL power optimization. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the ARM Connected Community, Cadence Connections program, the IEEE-­‐SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, and Si2, and it is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan, and North America. More information can be found at www.calypto.com..

Catapult, Calypto, PowerPro, and SLEC are registered trademarks of Calypto Design Systems Inc. All other trademarks are the property of their respective owners.

 

Media Contact:

Linda Marchant, Cayenne Communications for Calypto, 919-451-0776, Email Contact

 

Acronyms:

AMBA: Advanced Microcontroller Bus Architecture

AXI: Advanced eXtensible Interface

ESL: Electronic System Level

HLS: High Level Synthesis

RTL: Register Transfer Level

SoC: System on Chip

TLM: Transaction Level Modeling

 

 

Search Terms:

High-level synthesis

HLS ESL

C-based

Power optimization

Power reduction

RTL power optimization




Review Article Be the first to review this article


Featured Video
Jobs
Assoc Geographic Info Analyst for North Central Texas Council of Governments NCTCOG at Arlington, Texas
Geospatial Software QA Engineer for Applied Research Associates, Inc at Albuquerque, North Carolina
Upcoming Events
GeoBuiz Summit 2019 at Hotel Intercontinental, 888 Howard St San Francisco CA - Jan 14 - 15, 2019
PrecisionAg Vision Conference 2019 at Hyatt Regency Lake Washington Seattle WA - Jan 15 - 16, 2019
Defence Geospatial Intelligence (DGI) 2019 at Royal Lancaster London London United Kingdom - Jan 28 - 30, 2019
International LiDAR Mapping Forum 2019 at Hyatt Regency Denver Colorado Convention Center, 650 15th Street Denver CO - Jan 28 - 30, 2019
Penn State
Teledyne:



Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation TechJobsCafe - Technical Jobs and Resumes  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise