V2.0 Release with 60 comprehensive new rules & enhanced SystemVerilog support significantly improves complex bug detection early in design cycle
SUNNYVALE, Calif. – Dec. 6, 2012 – Real Intent, Inc., a leading provider of EDA software products today announced the version 2.0 release of its Ascent™ Lint tool for early functional verification. It adds 60 comprehensive rules including new FSM checks, while maintaining its analysis speed of 450M gates in less than one hour, with no need for hierarchical processing. Real Intent also added Verdi3 support for integration to this industry-leading debug platform from Synopsys (formerly SpringSoft). This new release maintains Real Intent’s product leadership in delivering what the company believes is the industry’s best-in-class RTL linter and design rule checker for full-chip SoC analysis.
Dr. Prakash Narain, president and CEO of Real Intent, said, “Real Intent is known as the company that accelerates early functional verification and advanced sign-off of electronic designs. Both the new rules we added and our enhanced support for SystemVerilog are good examples of our tireless efforts to help SoC designers achieve correct hardware designs. We consistently deliver the most effective verification solutions available to solve critical problems, with comprehensive error detection, low-noise reporting and high ROI. Customers already are applauding our important update to Ascent Lint.”
According to Michael Martin, director of engineering at Integrated Device Technology, "IDT is enjoying the advantages of the new Ascent Lint 2.0 release. Our comprehensive design rule-set is fully supported and it takes just a few minutes for runs to complete. The product is easy to use and debug is fast and efficient. Ascent Lint was easy to adopt into our production design flows and we really like the integration with the new Verdi3 debug platform from SpringSoft. For any issues we had, the technical support team at Real Intent was impressive.”
Expanded Rule Set and Language Support
Ascent Lint 2.0 delivers enhanced support for SystemVerilog, Verilog and VHDL languages, and improves ease of use in the GUI and low-noise reporting of design issues. The expanded rule set ensures design code quality and consistency for a wide range of potential issues. It covers:
- New FSM modeling checks and coding conventions
- Expanded checking of unsynthesizable constructs
- Coding that leads to functional errors or simulation-synthesis mismatches
- Mixing of different hardware description languages
Ascent Lint 2.0 is available immediately for download from the Real Intent web-site. For more information about Ascent Lint from Shiva Borzin, technical marketing manager at Real Intent, please visit: http://www.youtube.com/watch?v=Je0NEF6ynb4.
About Real Intent
Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. The company provides comprehensive CDC verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. Real Intent’s Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness. Please visit www.realintent.com for more information.
CDC: Clock Domain Crossing
EDA: Electronic Design Automation
FSM: Finite-State Machine
GUI: Graphical User Interface
IEEE Institute of Electrical and Electronics Engineers
RTL: Register Transfer Level
VHDL Very High-level Design Language
Ascent and Meridian are trademarks of Real Intent, Inc.
All other trademarks and trade names are the property of their respective owners.
Sarah Miller for Real Intent
ThinkBold Corporate Communications