Belgrade, Serbia – December 7th, 2012 - HDL Design House, provider of high performance digital and analog IP cores and SoC design and verification services, today announced availability of MIPI CSI-2 Transmitter (HIP 3900), digital core that is compliant with the MIPI Alliance CSI-2 Specification, as part of HDL Design House FlexIP core library. CSI-2 (Camera Serial Interface) transmitter IP core (HIP 3900) is highly configurable, synthesizable digital IP core which receives pixels from camera sensor, performs packing in form of CSI-2 long packets and short packets, and sends them via PPI interface to the Host processor. HDL Design House CSI-2 Tx IP core can be combined with CSI-2 Rx and D-PHY IP cores, also available from the FlexIP core library, thus providing a complete, single-vendor MIPI CSI-2 solution.
HIP 3900 is compliant with the following specifications: CSI-2 (Camera Serial Interface) version 1.01, D-PHY version 1.0, AMBA3 AHB-Lite Protocol Specification version 1.0. The AHB interface is used for configuration of CSI-2 transmitter IP core, allowing external access to the core's 32-bit configuration, status, power management, and interrupt registers. The PPI interface is used to transmit pixel and command from external D-PHY, using independent High Speed (HS) and Low Power (LP) TX data paths. When in LP mode, the CSI-2 Transmitter IP core is used for Ultra Low Power control. In HS mode, the data is received using between 1 and 4 data lanes. Camera Pixel Interface is used to directly connect Camera sensor with CSI-2 Transmitter IP Core. HIP 3900 is a configurable IP core with more than 30 configuration and interrupt registers.
HDL Design House CSI-2 Transmitter IP core (HIP 3900) supports up to 4 data lanes, one clock lane and up to 4 virtual channels. HIP 3900 supports High Speed, Low Power and Ultra Low Power modes. It supports various pixel formats defined in CSI protocol version 1.01: YUV420 8-bit, YUV420 8-bit (legacy), YUV420 10-bit, YUV422 10-bit, YUV420 8-bit (CSPS), YUV420 10-bit (CSPS), YUV422 8-bit, YUV422 10-bit, RGB888, RGB666, RGB565, RGB555, RGB444,RAW6, RAW7,RAW8, RAW10, RAW12, RAW14.
HDL Design House MIPI CSI-2 Transmitter IP core is available now, along with CSI-2 Rx and the silicon-proven MIPI D-PHY IP core in 65nm and 40nm.
HDL Design House has been a MIPI Alliance Contributor Member since 2010.
About HDL DH FlexIP core library
The FlexIP core library includes a broad portfolio of high-quality, silicon proven digital and analog IP cores for SoC designs. The library covers a large number of standards and protocols such as HDMI, DisplayPort, MIPI (M-PHY, D-PHY, DSI, UniPro and CSI, DigRF, BIF), USF, I2S, Serial RapidIO, SPI flash memory controller, PCI Express, SATA, USB 3.0, and others. Apart from the large number of supported protocols and standards, one of the greatest competitive advantage for users of the FlexIP core library is HDL Design House outstanding capabilities in providing integration services, customization of the IP core at customer's request, verification solutions for the given IP core, as well as on site support. For more information on the FlexIP core library, please go to http://www.hdl-dh.com/products.html
About HDL Design House
HDL Design House delivers leading-edge digital and analog design and verification services and products in numerous areas of SoC and complex FPGA designs. The company also develops IP cores and offers back-end services. The company has extensive experience with the ARM CPU architecture, ARM CPU processor interfaces and development or integration of SoC based on ARM CPU. Founded in 2001 and currently employing 60 engineers working in two design centers in Serbia, HDL Design House mission is to deliver high quality products and services, with flexible licensing models, competitive pricing and responsible technical support. The company was awarded ISO 9001:2000 and ISO 27001:2005 certifications in December 2006/2009. For more information, please visit www.hdl-dh.com
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