This announcement follows on the heels of recent announcements from other organizations to utilize FD-SOI technologies. Moore's Law -- the observation that the number of transistors on a chip doubled about every two years -- has driven the semiconductor industry over the past 50 years to shrink the size of the transistors, which are essentially miniature on/off switches. The increased density from these size reductions have given consumers the explosion of new and more exciting features at lower-cost that we've come to expect. In parallel, these new features are able to operate at clock speeds that allow the phones to respond to your commands -- by keypad, touchpad, and now voice -- almost before you finish expressing the command.
Now, as those transistors shrink to nanoscale dimensions where about 450 transistors can fit within the diameter of a human hair, physics are challenging the traditional high-speed and low-power advantages of planar CMOS technology manufactured on bulk silicon wafers. FD-SOI technology is a major breakthrough in the pursuit of miniaturization of electronic circuits, and the achievement of 3GHz operating speed for an application-processor engine presages the adoption of FD-SOI in portable equipment, digital still cameras, gaming and ASICs for a range of applications. Of the next-generation process technologies, FD-SOI alone has proven its ability to meet the industry's highest performance and lowest power demands that are vital to delivering graphics and multimedia that amaze without sacrificing battery life.
"As we had anticipated, FD-SOI is proving to be fast, simple and cool; we had fully expected to see 3GHz operating speeds, the design approach is very consistent with what we had been doing in bulk CMOS, and, with the benefits of fully depleted channels and back biasing, the low-power requirements are also meeting our expectations," said Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, and Chief Technology and Manufacturing Officer of STMicroelectronics.
Reinforcing the point of simplicity, ST has found porting Libraries and Physical IPs from 28nm Bulk CMOS to 28nm FD-SOI to be straightforward, and the process of designing digital SoCs with conventional CAD tools and methods in FD-SOI to be identical to Bulk, due to the absence of MOS-history-effect. FD-SOI enables production of highly energy-efficient devices, with the dynamic body-bias allowing instant switch to high-performance mode when needed and return to a very-low-leakage state for the rest of the time -- all in a totally transparent fashion for the Application Software, Operating System, and the Cache Systems. Finally, FD-SOI can operate at significant performance at low voltage with superior energy efficiency versus Bulk CMOS.
ST will be demonstrating the FD-SOI technology at its booth (Hall 7 E110) at Mobile World Congress in Barcelona, Feb 25-28.
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 FD-SOI transistors have a drawn channel length of 28nm and a pitch (transistor to transistor) of 113nm, allowing almost 450 transistors to fit across a 50,000nm-diameter human hair.
ST 28nm FD-SOI Technology Hits 3GHz_FINAL:
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