DuART, tiny UART IP Core from Digital Core Design

March 13, 2013 -- DμART, the newest IP Core mastered by Digital Core Design, is one of the tiniest UART IP Cores available on the market. Small is beautiful, that’s why DCD’s tiny works not only in UART mode, but also implements separate BAUD clock line, false start bit detection, status report and internal diagnostic capabilities.

The DμART is a soft core of a Universal Asynchronous Receiver/Transmitter (UART). It can perform both, serial-to-parallel conversion on data characters received from a peripheral device or a modem and parallel-to-serial conversion on data characters received from the CPU. The CPU itself can read the complete status of the UART at any time during the functional operation. Reported status information includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions, like overrun or framing.



The DμART includes also a programmable baud rate generator – says Jacek Hanke, CEO at Digital Core Design -   which is capable of dividing the timing reference clock input by divisors of 1 to (216-1) and producing a 16 × clock, for driving the internal transmitter logic. Provisions are also included to use this 16 × clock, to drive the receiver logic. The newest UART Core from Digital Core Design has been also equipped with a processor-interrupt system. Thanks to it, the interrupts can be programmed according to the user's requirements, minimizing the computing required to handle the communications link.

The DμART core is perfect for applications, where the UART and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. DCD’s solution is also suitable for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices as well.

More information & data sheet at  http://dcd.pl/ipcore/690/duart/ .





Read the complete story ...


Review Article Be the first to review this article
HP

Harris

Featured Video
Jobs
Imagery Analyst for ARA at Albuquerque, NM -1229, NM
Sr. GIS Technical Analyst for Southern California Edison SCE Transmission and Distribution Organization at Rosemead, CA
Inside Sales for SolidCAM at Newtown, PA
Director of Mechanical Engineering for Velodyne LIDAR at Morgan Hill, CA
Architetural Project Manager for DRA Architects at Irvine, CA
Architect for North County Transit District at Oceanside, CA
Upcoming Events
2017 GIS/CAMA Technologies Conference at Chattanooga Convention Center Chattanooga Tennessee - Mar 6 - 9, 2017
IGTF 2017 ASPRS Annual Meeting 2017 at Marriot Waterfront Baltimore Baltimore MD - Mar 11 - 17, 2017
MAPPS Federal Programs Conference at Sheraton Hall Silver Spring Maryland - Mar 13 - 15, 2017
WorldCover 2017 Conference at ESRIN Italy - Mar 14 - 16, 2017
GENEQ
Teledyne Optech
Teledyne:
xponential2017
CADalog.com - Countless CAD add-ons, plug-ins and more.



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation TechJobsCafe - Technical Jobs and Resumes  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy