DSPI_FIFO – SPI master slave enhanced with detectors

Digital Core Design, IP Core provider and a System on Chip design house has presented the newest SPI IP Core enhanced with useful design features. The DSPI_FIFO is a fully configurable SPI master/slave device, which allows to configure polarity and phase of a serial clock signal SCK. DCD’s core enables microcontroller to communicate with serial peripheral devices, but also to communicate with an interprocessor in a multi-master system. It supports all the features of SPI and transmission/reception FIFOs, to significantly reduce the CPU time.

Bytom, 7thof November 2013--The DSPI_FIFO system is flexible enough, to interface directly with numerous standard product peripherals, even from several manufacturers. The system can be configured as a master or as a slave device, with data rates as high as CLK/4. The clock control logic allows to select clock polarity and choose two fundamentally different clocking protocols, to accommodate most available, synchronous serial peripheral devices. When the SPI is configured as a master, the software selects one of eight different bit rates for the serial clock. –A serial clock line (SCK) synchronizes shifting and sampling of the information on two independent serial data lines – explains JacekHanke, CEO at Digital Core Design – so the data is simultaneously transmitted and received.

The DSPI_FIFO automatically drives selected by the SSCR (Slave Select Control Register) slave outputs (SS7O – SS0O) and addresses the SPI slave device to exchange serially shifted data. Error-detectionlogic is included to support interprocessor communication.
A write collision detector indicates, when an attempt is made to write data to the serial shift register, while a transfer is in progress. A multiple-master mode-fault detector automatically disables DSPI output drivers, if more than one SPI device simultaneously attempts to become a bus master.

The DSPI_FIFO supports two DMA modes: single transfer and multi-transfer. These modes allow the DSPI_FIFO to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.

DCD’s IP Core is technology independent and silicon proven design. It is fully customizable, which means it is delivered in the exact configuration of customer’s requirements. - There is no need to pay extra for not used features and wasted silicon – ends Hanke. The DSPI_FIFO includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.

More information:

http://dcd.pl/ipcore/125/dspi-fifo/

Key features:

  • SPI Master
    • Master and Multi-master operations
    • Two modes of operation: SPI mode and FIFO mode
    • 8 SPI slaveselect lines
    • System error detection
    • Modefault error
    • Write collision error
    • Interruptgeneration
    • Supports speeds up 1/4 of system clock
    • Bit rates generated 1/4 - 1/512 of system clock.
    • Four transfer formatssupported
    • Simple interface allows easy connection to microcontrollers
  • SPI Slave
    • Slaveoperation
    • Two modes of operation: SPI mode and FIFO mode
    • System error detection
    • Interruptgeneration
    • Supports speeds up 1/4 of system clock
    • Simple interface allows easy connection to microcontrollers
    • Four transfer formatssupported
  • Fullysynthesizable
  • Two DMA Modes allows single and multi-transfer
  • In the FIFO mode transmitter and receiver are each buffered with 16/64 byte FIFO's to reduce the number of interrupts pre-sented to the CPU
  • Optional FIFO size extension to 128, 256 or 512 Bytes
  • Available system interfacewrappers:
    • AMBA - APB Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus
  • Staticsynchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Versatileinterrupt system:
    • Single interrupt output with eight maskable interrupting conditions
    • Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs
    •  Each FIFO can be programmed for four different interrupt levels
    • Watch dog timer for each receiver
  • Automatic wake-up mode for multidrop applications
  • Start-end breakinterrupt/status
  • Detects break which originates in the middle of a character
  • Power down mode
  • Receivertimeoutmode

Information about Digital Core Design:

Digital Core Design is a leading Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house. The company was founded in 1999 and since the early beginning has been considered an expert in IP Core architecture improvements. Thousands of customers became convinced by our unique solutions and billions of people worldwide use our technology in USBs, MP3 players, mobile phones and many other applications.

The innovativeness of DCD's IP solutions has been confirmed by over 500 licenses sold to over 300 customers worldwide, such as: INTEL, SIEMENS, PHILIPS, TOYOTA, OSRAM, GENERAL ELECTRIC, SILICON GRAPHICS, RAFAEL, SAGEM or GOODRICH.

More information: http://dcd.pl/page/147/about/



Contact:

Tomeq Cwienk,
Digital Core Design,
ul. Wroclawska 94,
41-902 Bytom, Poland
skype: tomasz.cwienk,
Tel: + 48 32 282 82 66 ext.25,
Mail to: Email Contact




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