AMIQ EDA Releases Version 3.5 of the Design and Verification Tools (DVT) IDE

AMIQ EDA announces version 3.5 of its flagship solution – DVT Eclipse IDE. The new version provides enhanced compilation, improved UVM support, and a streamlined GUI to help design and verification engineers increase code development quality and productivity. It also offers a set of capabilities that simplifies DVT deployment.

March 3, 2014, San Jose, CA – AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification, today announced the release of version 3.5 of the Design and Verification Tools (DVT) IDE. This version brings enhanced compilation, improved UVM support, a streamlined GUI, and capabilities that simplify DVT deployment. 

The DVT IDE is a complete and powerful code development environment for the design and verification languages e, SystemVerilog, Verilog, VHDL. It is built on the Eclipse Platform and includes an IEEE standard-compliant parser, which continuously runs in the background. The tool integrates within a single window a smart code editor with a comprehensive set of features that help with code inspection, navigation, documentation, and debugging. It also includes an innovative linting framework, supports the Universal Verification Methodology (UVM), and enables engineers to build UVM-compliant environments effortlessly.

The key enhancements and new capabilities that DVT version 3.5 brings to its users include:

Enhanced compilation for SystemVerilog and VHDL

The internal compiler now checks on the fly whether each identifier is properly declared and used. This enhancement further reduces the number of compilation cycles required to get compilation error-free code as you type.

Improved UVM Support

The newly added capabilities simplify browsing the structure of an UVM-based verification environment. Users will benefit from:

  • UVM Browser View that helps explore the UVM classes grouped by categories such as agents, drivers, and sequences as well as easily inspect the UVM flow-specific API like overridden phases and fields registered to the factory.
  • Verification Hierarchy View, which lets the user see the top-down topology of an UVM verification environment based on UVM factory “create” calls.
  • UVM Factory Queries for "config db setters", "config db getters", and "factory overrides" that help quickly and accurately locate UVM factory-related constructs that may influence the behavior of a testbench.

Redesigned tool configuration and preference sharing capabilities

A new out-of-the-box Settings Management Engine simplifies DVT deployment for large teams. Settings are organized in several easily customizable precedence levels such as project, user, and common in order to allow fine-grained control.

Streamlined GUI experience

Version 3.5 introduces new features and enhancements like:

  • Content Filters that help eliminate irrelevant information displayed in Views such as compilation issues, in-line reminders, or internal API introduced by 3rd party libraries like UVM.
  • The popular Quick Search bar, which allows users to easily locate a specific element by typing a few letters from its name, is now available in all Views.
  • A completely unified feature set across all languages in the DVT Perspective – the visual container for the various Views and components within the DVT window. For example, Check View and Coverage View can now be used in both e language and SystemVerilog projects.
  • Redesigned icons, toolbars, and menus.
  • Simplified trace drive and trace load.

Other enhancements available in DVT 3.5

  • Improved compilation performance and errors recovery.
  • A more robust and customizable code-formatting engine.

The new enhancements and capabilities added in DVT version 3.5 will further help design and verification engineers overcome the limitations of plain text editors and benefit of the advanced features of a totally integrated code development solution that works across languages, enabling them to:

  • Increase the speed and quality of new code development
  • Simplify the maintenance of legacy code and reusable libraries
  • Manage effectively multi-language projects
  • Accelerate language and methodology learning
  • Build UVM-compliant verification environments
  • Cope easier with increasingly complex hardware

AMIQ EDA is exhibiting at DVCon, Booth 704, on March 3 – 5, 2014, in San Jose and showcasing DVT version 3.5.  

AMIQ EDA focuses on adding value to the design and verification domains through its proprietary code development and analysis tools.  Since 2006, its core solution – Design and Verification Tools (DVT) – the first IDE for the e language, SystemVerilog, and VHDL, has helped engineers increase the speed and quality of code development and simplify debugging, enabling them to complete their projects faster. Its newer product – Verissimo SystemVerilog Testbench Linter – allows verification groups to improve testbench code reliability and functionality as well as implement best coding practices and their own specific guidelines. For more information about AMIQ EDA and its solutions, visit  

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