DVCon Europe Call for Tutorials Deadline June 1




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The Design and Verification Conference & Exhibition Europe ( DVCon Europe) is the premier conference for system architects, concept engineers, software developers, design and verification engineers, and IP integrators to share the latest methodologies and technologies on the practical use of EDA and IP languages and standards used in electronic design.

The focus of this highly technical conference is on the industrial application of specialized design and verification languages such as SystemC, SystemVerilog, VHDL, UVM or e; assertions in SVA or PSL; the use of AMS languages; design automation using IP-XACT; and the use of general purpose languages C and C++.

Call for Tutorials

This Call for Tutorials solicits high quality educational training sessions that are technical and reflect real life experiences in using EDA languages, standards, methodologies and tools. Industry applications of interest are (but not limited to) automotive, mobile communication, aerospace, healthcare, chip-cards, consumer and power electronics. Submissions are encouraged in (but not restricted to) the topic areas listed below.

  • Electronic System Level (ESL) design including: architectural and algorithmic exploration; interface-based design; transaction level modeling (TLM), etc.
  • SystemC (or more generally, C/C++ based) for design, verification and/or high level synthesis.
  • Hardware/software co-design or and co-verification, acceleration or emulation.
  • Mixed-signal design and verification using SystemC-AMS, Verilog-AMS, VHDL-AMS, etc.
  • Using SystemVerilog and/or the Universal Verification Methodology (UVM) for functional and coverage-driven verification.
  • Verification and validation methodologies, verification management and/or traceability.
  • Assertion-based Verification (e.g., SystemVerilog Assertions, PSL, etc.)
  • Low-power design techniques using standards like UPF, CPF, IEEE1801, etc.
  • Design or verification for functional safety (e.g., ISO 26262, DO-254).

DVCon Europe tutorials are 90 minute sessions, which will be presented on November 11, 2015. Concerning the tutorial structure, there is the option to have a single speaker for the session, but it is also possible to have several speakers. The submitter is in both cases responsible to organize the tutorial and deliver the presentation material.

Please submit your 500-600 word tutorial abstract by June 1, 2015. Full instructions and details for the abstract and tutorial submission process can be found on www.dvcon-europe.org

Call for Papers still open

The Call for Papers is still open! Please submit your draft version of the paper by May 1, 2015. Detailed instructions on the paper requirements and submission process can be found on www.dvcon-europe.org

General Chair: Martin Barnasconi, NXP Semiconductors
Vice Chair: Oliver Bell, Intel
Finance Chair: Yatin Trivedi, Synopsys
Program Chair: Matthias Bauer, Infineon Technologies
Poster Chair: Mike Bartley, TVS
Tutorial Chair: Joachim Geishauser, Freescale
Promotion Chair: Dave Kelf, OneSpin Solutions

DVCon Europe conference management is provided by the Electronic Chips and Systems design Initiative ( ECSI).

Feel free to contact us for questions on the submission process: Email Contact or visit www.dvcon-europe.org


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