Collaboration ensures that Aprisa and Apogee will be ready for joint customers to start evaluations/ /designs for 10nm process node
SANTA CLARA, Calif. — (BUSINESS WIRE) — April 6, 2015 — ATopTech, the leader in next generation physical design solutions, is collaborating with TSMC to certify Aprisa and Apogee, ATopTechs place and route solutions, for TSMC 10nm process technology. ATopTech has long collaborated with TSMC for advanced processes, starting with 28nm and 20nm and moving through 16FinFET (16FF) and 16FinFET+ (16FF+). The success of this continuing collaboration has resulted in ATopTech being designated as a Partner of the Year by TSMC in 2012, 2013 and 2014.
Our continuing collaboration with TSMC at 10nm ensures that Aprisa and Apogee will be ready for joint customers to start evaluations and designs for the 10nm process, giving them an advantage in automatic place-and-route, said Jue-Hsien Chern, CEO of ATopTech. As always, it is our pleasure to work with TSMC to ensure the highest possible routability for leading-edge technology nodes.
Aprisa is a complete place-and-route (P&R) engine, including placement, clock tree synthesis, optimization, global routing and detailed routing. The core of the technology is its hierarchical database. Built upon the hierarchical database are common analysis engines, such as RC extraction, DRC engine, and an advanced, extremely fast timing engine to solve the complex timing issues associated with OCV, signal integrity (SI) and multi-corner multi-mode (MCMM) analysis. Aprisa uses state-of-the-art multi-threading and distributed processing technology to further speed up the process. Because of this advanced architecture, Aprisa is able to deliver predictability and consistency throughout the flow, and hence faster total turn-around time (TAT) and best quality of results (QoR) for physical design projects.
Apogee is a full-featured, top-level physical implementation tool that includes prototyping, floorplanning, and chip assembly. The unified hierarchical database enables a much more streamlined hierarchical design flow. Unique in-hierarchy-optimization (iHO) technology helps to close top-level timing during chip assembly through simultaneous optimization at top level and at blocks, reducing the turnaround time for top-level timing closure from weeks to days.
ATopTech, Inc. is the technology leader in IC physical design. ATopTechs technology offers the fastest time to design closure focused on advanced technology nodes. The use of state-of-the-art multi-threading and distributed processing technologies speeds up the design process, resulting in unsurpassed project completion times. For more information, see www.atoptech.com.
Aprisa and Apogee are trademarks and ATopTech is a registered trademark of ATopTech, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.
Cayenne Communication LLC
Michelle Clancy, 252-940-0981