TEWKSBURY, Mass. — (BUSINESS WIRE) — June 8, 2015 — Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of DDR4 3D Stacking (3DS) support for its DDR4 memory chip and LRDIMM Verification IP (VIP) models and compliance testsuites.
DDR-Xactor VIP supports
- SDRAM memory chip models
- RDIMM/LRDIMM models including RCD and DB
- DFI-PHY model
- Memory controller model including initialization, training, and auto sequencing commands
- I2C models
- RDIMM/LRDIMM compliance testsuite
- Timing and protocol checks
- Functional coverage on MRS, RCD, DB register configurations, DDR and LRDIMM address accesses, FSM states, and errors
- DFI and JEDEC protocol analyzer trackers
Models and compliance testsuites are developed 100% in SystemVerilog and UVM.
Memory models support all speed modes and configurations including parameter files for the major SDRAM and RDIMM/LRDIMM vendors including Samsung and Micron. Memory models support a full SDRAM/DIMM user API with many advanced features not included in many “free” models such as
- Clock jitter
- Random DQS timing
- CRC/parity error injection
- Backdoor access to DDR chip and DIMM memory locations
- Callbacks and analysis ports for memory access and state transitions
RDIMM/LRDIMM-level verification is performed using the Avery provided plug’n’play testbench and compliance testsuite focusing on RCD and DB functional and overall timing requirements.
SoC/memory controller verification is performed using the Avery DDR chip/DIMM memory models to test memory controller functions such as memory refresh and control modes such as DDR4's PDA and modereg readout.
DDR-Xactor supports the JEDEC SDRAM standards including DDR4, DDR3, and the JEDEC mobile memory standards including LPDDR4 and LPDDR3, and DRAM module standards for RCD and DB. DDR-Xactor also supports the DFI-PHY 3.1 standards.
“DDR4 memory systems are significantly more challenging to get right than in previous generations. Avery is in a position to assist memory controller, PHY, and RDIMM/LRDIMM makers with the robust models, timing and protocol checking, and compliance testsuites for comprehensive functional verification and performance tuning,” says Chilai Huang, president of Avery Design Systems.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, UFS, MIPI, DDR/LPDDR, HMC, ONFI/Toggle, NVM Express, SCSI Express, SATA Express, eMMC, SD/SDIO, and CAN FD standards. The company is a member of the Mentor Graphics Value Added Partnership (VAP) program and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
Avery Design Systems
Chris Browy, 978-851-3627