Power integrity @ DesignCon 2016


Two more weeks before DesignCon 2016!

Jan 6, 2016 -- DesignCon may appear package- and PCB-focused only, but it's actually also covering SoC related power integrity topics, and as DesignCon 2016 is a great opportunity to meet old friends and colleagues to discuss on-chip Dynamic Voltage Drop and in-rush current challenges, we will be there too; ready to discuss the latest and greatest on how we can improve on-chip power integrity.

In case you haven’t considered DesignCon yet, or even checked the program, note that there are a couple of really interesting sessions on power integrity. We have compiled all the details of these sessions so you can look at the descriptions, who the presenters are etc. 

Go  HERE to download the single PDF file with the full details and description.  

Wednesday Jan 20th

  • Impacts of Dynamic Noise in Multi-Core or SOC Designs 
  • Evaluation of PDN coupling on SOC 
  • A Novel Power-Supply-Induced-Jitter Suppression Technique for High-Speed Interface Using Modulated-PDN 

Thursday Jan 21st 

  • A Frequency Domain Approach to Transient Result for Power Distribution Network Analysis 
  • Block-Level Modeling Based Power and Signal Integrity Performance Optimization of Integrated Core and Memory System 
  • PDN Prototyping and Optimization at an Early Design Stage 

 



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