Si2's Low Power Coalition Announces CPF Roadmap

AUSTIN, Texas—(BUSINESS WIRE)—February 22, 2008— Silicon Integration Initiative (Si2) today published the Low Power Coalition's (LPC) approved Roadmap for Common Power Format (CPF) extensions planned out through mid-2009, along with a Request for Technology (RTF) to support the CPF extensions as well as power/design flow-related requirements. This announcement underscores the vitality and relevance of the LPC work as it continues to evolve based on designer and end-user needs (see member list below).

The announced CPF extensions cover the following items - a detailed presentation of each item can be found at this link: http://www.si2.org/?page=928

Immediate - Requirements for CPF Version 1.1 (target release - mid 2008)

-- Hierarchical flow support.

-- Memory modeling styles and support.

-- Gate-level verification flow CPF support.

-- Power estimation support

-- Clocking and related updates required to drive power optimization.

Medium Term - Requirements for CPF 1.2 (target release - early 2009)

-- Pre-Si and post_Si power modeling and budgeting.

-- Test power definitions not represented in CPF.

-- Investigate Load_foreign.

-- IO modeling and representation.

Long Term - Requirements for CPF 2.0 (target release - mid 2009)

-- CPF to drive debug related to power.

-- CPF based system level definition.

While the above items are an excellent start, they are recognized as only a start and will benefit from additional evolution and extension. It is also recognized that useful technologies exist in various companies in the industry. Those companies may be interested in being recognized for their technologies in various parts of the design flow from very high level all the way to the physical level. Sharing technologies and structures through the LPC can lead to faster industry progress and convergence. To that end, the LPC, with the assistance of Si2, has issued the Request for Technology, which is located at: http://www.si2.org/?page=784

Background

The CPF standard was approved and made publicly available in March of 2007, and since then has achieved wide acceptance in EDA tool adoption, use in end-user tool flows, numerous completed chip tape-outs and subsequent testimonials, and adoption into major foundry reference flows. In addition to the CPF 1.0 standard document (868 downloads) and CPF tutorial (625 downloads), adoption aids include CPF Parser software (53 downloads) and a CPF Pocket Guide (1310 downloads), all freely available from Si2. CPF is also supported by members of the Power Forward Initiative, www.powerforward.org

Within the next couple of weeks, a new CPF Relational Analyzer will be announced - another valuable (and free) adoption aid.

About the Low Power Coalition (LPC)

The Low-Power Coalition (LPC) is delivering enhanced capabilities in low-power Integrated Circuit (IC) design flows in particular relating to specifications of low-power design intent, architectural tradeoffs, logical/physical implementation, design verification and testability. Member companies are: Advanced Micro Devices (NYSE: AMD), ARM (Nasdaq: ARMHY), Atrenta, Azuro, Cadence Design Systems (Nasdaq: CDNS), Calypto Design Systems, ChipVision Design Systems, Entasys, Freescale Semiconductor, IBM (NYSE: IBM), Intel (Nasdaq: INTC), LSI Logic (NYSE: LSI), NXP Semiconductors, Sequence Design, and Virage Logic (Nasdaq: VIRL). For further information on the Low Power Coalition, see www.si2.org/?page=726

About Si2

Si2 is an organization of industry-leading semiconductor, systems, EDA, and manufacturing companies focused on improving the way integrated circuits are designed and manufactured in order to speed time to market, reduce costs, and meet the challenges of sub-micron design. Si2 is uniquely positioned to enable collaboration through a strong implementation focus driven by its member companies. Si2 focuses on developing practical technology solutions to industry challenges. Si2 represents companies involved in all parts of the silicon supply chain throughout the world. www.si2.org

All trademarks are the property of their respective owners.

Contact:

Silicon Integration Initiative (Si2)
Bill Bayer, 512-342-2244 ext.304


Rating:


Review Article Be the first to review this article
Trimble

Harris

Jobs
Geospatial Analyst - Senior for BAE Systems Intelligence & Security at Springfield, VA
Geospatial Systems Administrator for BAE Systems Intelligence & Security at arnold, MO
Senior Mechanical Engineer for BAE Systems Intelligence & Security at Arlington, VA
Mechanical Design Engineer 3 for KLA-Tencor at Milpitas, CA
Sr Mechanical Design Engineer for Medtronic at mounds view, MN
Urban Designer - Urban Design/Planning for SERA Architects, Inc at Portland, OR
Upcoming Events
Geospatial World Forum 2018 at Hyderabad International Convention Centre Hyderabad India - Jan 16 - 19, 2018
2018 Annual Convention of Virginia Association of Surveyors at 24 S. Market St Staunton VA - Jan 18 - 20, 2018
ArcGIS: Introduction at Environmental and Natural Resource Building 14 College Farm Rd New Brunswick NJ - Feb 1 - 22, 2018
International LiDAR Mapping Forum at Hyatt Regency 650 15th Street, Denver CO - Feb 5 - 7, 2018
Teledyne Optech
CADalog.com - Countless CAD add-ons, plug-ins and more.



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation TechJobsCafe - Technical Jobs and Resumes  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise