In April, Virage Logic was the first commercial IP provider to release its 40-nanometer (nm) SiWare product portfolio on TSMC’s 40nm manufacturing process with memory compilers and logic libraries. Virage Logic now is also the first commercial IP provider to support TSMC’s Power Trim Service, announced at the TSMC symposium in April 2008.
Virage Logic extends the inherent power-management benefits of SiWare IP to cover TSMC 65nm and 90nm process nodes while offering early access to design more competitive chips with reduced leakage power and significant cost savings. With its advanced tradeoff capabilities, SiWare Memory users can achieve static power savings of up to 35 percent, 70 percent or 90 percent depending on their selection of the built-in light sleep, deep sleep and shut-down modes available in 40nm memories.
“Being first to market with commercial IP tailored for the Power Trim Service reflects our close collaboration with TSMC to support advanced manufacturing processes,” said Brani Buric, vice president of product marketing and strategic foundry relationships, Virage Logic. “For more than a year, Virage Logic has been a TSMC early development partner at 40nm. We’re honored to build on our trusted partnership to address the SoC design community’s need for low power solutions that meet the stringent demands of advanced geometries and help them proceed with confidence to the next process node.”
“It’s the designer who benefits most,” said S.T. Juang, senior director of design infrastructure marketing at TSMC. “With Virage Logic’s SiWare 40nm IP supporting our Power Trim Service, designers enjoy the benefits of low-power design optimization at the 40nm process technology.”
About TSMC’s Power Trim Service
TSMC’s Power Trim Service overlays manufacturing design technology software and advanced semiconductor process technology to tune manufacturing chip design. Power Trim uses software developed by Blaze DFM that identifies design paths with sufficient timing “slack” and optimizes transistors along these paths without reducing chip performance. The software generates a marker layer that identifies transistors for special handling during TSMC’s Optical Proximity Correction process. This special handling produces slightly slower transistors with significantly less leakage. The leakage power reduction from adjusting an individual transistor is relatively small; when accrued over the tens or hundreds of millions of transistors in a chip, the overall reduction is significant. This fine-grained optimization process results in substantially lower leakage power consumption for the entire design.
Power Trim is fully compatible with, and may be used in conjunction with, all other leakage reduction techniques such as multi-Vt cell libraries, reverse body biasing, header/footer sleep switches, and voltage islands. It provides additional leakage improvements over and above what can be achieved with these other techniques, and requires no major changes to the customer’s existing design flow, design signoff, or hand-off to manufacturing. No existing design tools need be replaced, and no changes to chip architecture, cell libraries, intellectual property blocks, logic design or physical layout are required.
Power Trim Advantages
TSMC validated Power Trim’s saving on both internal and customer designs. It delivered sizable reductions in average leakage power and significant impacted leakage variability on cell-based digital design. The corresponding increase in parametric yield can mean substantial cost savings.
Two commercial designers have already used Power Trim and others are being added selectively during a phased rollout.
About Virage Logic’s SiWare Memory Compilers and SiWare Logic Libraries
The SiWare Memory product line of silicon aware compilers provides power-optimized memories for advanced processes at 65nm. These high-performance memory compilers minimize both static and dynamic power consumption and provide optimal yields. SiWare High-Density memory compilers are optimized to generate memories with the absolute minimum area. SiWare High-Speed memory compilers are designed to help designers achieve the most aggressive critical path requirements. Compile-time options for process threshold variants, power saving modes, read and write margin extensions, ultra-low voltage operation, and innovative design for at-speed test enable SoC designers to configure optimal solutions for their specific design requirements.
The SiWare Logic product line includes yield-optimized standard cells
for a wide variety of design applications at 65nm with multiple
threshold process variants. SiWare Logic libraries are offered using
three separate architectures to optimize circuits for
Ultra-High-Density, High-Speed, or general use. SiWare Ultra-Low-Power
extension libraries provide designers with the most advanced power