Verification Special Session at DAC 2009 to Discuss Advances in Debugging

MUNICH & MOUNTAIN VIEW, Calif. — (BUSINESS WIRE) — July 29, 2009 A panel of EDA industry experts representing leading-edge companies and world-renowned universities will address recent advances to ease and speed property and design debugging, in a special session at this year’s DAC. Debugging of RTL that failed verification is the largest manual burden in chip design today. It takes 30 to 35% of the total design time as it adds uncertainties and costs. A failure trace returned in simulation, property checking and assertion-based methods is not enough – leaving users with the question “Okay, where is the bug?” and an often lengthy debugging session. Productivity is stymied until the bug is found, often involving time-consuming iterations between verification and design engineers. This special session chaired by Eli Singerman of Intel Corp. and organized by Rolf Drechsler of the University of Bremen will tackle such issues as tool advances to accelerate root cause analysis of failures, automation in RTL and post-silicon debug, how formal techniques can speed debugging, and RTL debugging techniques based on information from higher abstraction levels. Six short papers will be presented, and a half-hour interactive discussion will wrap up the session.

PANELISTS:

--   Gila Kamhi, Principal Engineer, Intel
-- Rajeev Ranjan, CTO, Jasper Design Automation
-- Adriana Maggiore, Principal Application Engineer, OneSpin Solutions
-- Masahiro Fujita, Professor, University of Tokyo
-- Andreas Veneris, Professor, University of Toronto
-- Valeria Bertacco, Professor, University of Michigan
 

WHEN:

Thursday, July 30, 2009, 9 - 11 a.m.

 

WHERE:

Moscone Center, Room 133
747 Howard Street
San Francisco, CA 94103
 

WHY:

Although verification is well understood and handled by many automated approaches, debugging is fast becoming a bottleneck to productivity. Come learn more from the experts about how to find bugs efficiently.

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