Breker Verification Systems’ Trek Selected by STMicroelectronics for Functional Verification Reuse

Austin, TX. February 2010 (Businesswire) – Breker Verification Systems, a private supplier of EDA software for functional verification, announced that STMicroelectronics, a global leader in developing and delivering leading edge Systems-on-Chip (SoC) products, has selected Trek to verify complex designs. Trek’s scenario model based testbench automation technology is providing a streamlined solution for automatically generating test stimulus, checking results and providing coverage closure to verify complex chips including cutting edge SoC designs.

ST performed a comprehensive evaluation of testbench automation technologies and chose Trek because of the efficient development and flexible use of verification scenario models. Some Trek based models have since been deployed into production projects providing immediate positive impact. With easy to understand constructs, graph-based models allow systematic decomposition of functional verification objectives, reduce testbench development time, provide efficient coverage closure measurement and support easy vertical reuse between unit level and system level verification. In the SoC context, IP-Core scenario models can be combined to generate C-code suitable for stressing the complete SoC design.

“ST welcomes new technologies that increase verification efficiency. Focusing on rapid development, use and reuse of verification models, Trek provides a solution that is complementary to ST’s existing verification flow. It is advantageously replacing directed scenario modeling by graphs, and comes with implicit scenario coverage metrics. Trek is reducing development time, improving coverage and easing communication between the various verification stakeholders,” said Olivier Haller, Verification Methodology Manager at STMicroelectronics. “By allowing verification models to be shared between block level and SoC level testbenches, the Trek technology will help to achieve a higher level of verification on SoC designs and provide a 2-3X reduction of effort.”

“Continuing to attract industry leaders like STMicroelectronics highlights the depth of the Breker solution,” said Adnan Hamid, CEO of Breker Verification, “With design complexity growing, a more efficient technique for communication, automation and reuse is needed to improve the verification effort. Trek is that solution.”

** About Breker Verification Systems **

Breker Verification Systems is an EDA company offering scenario model based test bench automation technology designed to drive existing functional verification test-benches. Complex verification intent is described as a simple yet concise scenario coverage model. The coverage model is used as input to automatically generate functional stimulus, check results and close coverage. Analytical capabilities include interactive visual rendering of pre-simulation reachability analysis and post simulation coverage analysis. Automating the generation of stimulus, results checks and coverage analysis is can reduce test-bench development time by a factor of 10x, resulting in a 2-3x reduction in overall verification schedules.

Privately held, Breker was founded in 2003 in Austin, TX. Its corporate headquarters is at 8217 Edgemoor Place, Austin, Texas 78749. Telephone: (512) 415-1199. On the Web at www.brekersystems.com

 

 

 


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