EDAptability: 100 % RTL @ Speed FPGA debugger
Groundbreaking technology opens new ways for signal visibility
MUNICH, Germany, October, 4th, 2007 - EDAptability today announced the availability of its new “intelligent Built in Streamer (iBiS)”. It can be seen as the most advanced debug approach for FPGAs and ASICs. Like no other comparable methodologies, it combines RTL elaboration, RTL modification, RTL model extraction and simulation techniques.
The tool offers 100 % RTL signal visibility and at speed debugging, so you can have freely running clocks without the need to slow them down for debugging. No re-synthesis is needed for debugging and the initially implemented general debug structure has no impact on timing or on the combinatorial logic. Only one fraction of the design is post-simulated starting from a timepoint shortly before the bug or the timezone of interest, even if the test already runs for hours before. The signals with their original names and types can be viewed with EDAptability's VCD viewer or any other third party VCD viewer.
The plug and play streamer enables direct data streaming and complex on-FPGA memories become obsolete. The streamer can also work as Altera and Xilinx FPGA download cable. The streamer capabilities can also be used as a data link btw. the FPGA and the workstation/PC.
Pricing and Availability
EDAptability's SynEDA 4.0 ibis feature includes the 100 % RTL @ speed FPGA debugger and a VCD viewer. The one-year-one-host license is priced at 8000 ï¿½ and is available. The streamer hardware is priced at 600 ï¿½.
EDAptability provides leading edge EDA tools for the complete ASIC and FPGA market. EDAptability's key technologies reach from unique simulator techniques to RTL-to-RTL partitioner techniques as well as outstanding system prototyping hardware. Each component can be seen as ahead of the competitors. For more information visit
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