IP Standards: No room for Mr. Nice Guy
Ian Mackintosh: In terms of standards bodies, it’s already happening – it’s already taken place. There are experimental models where people have played around with this in Japan, China, and Hong Kong. It will expand beyond this level simply because a lot of people want to remove internal costs by sharing the costs of the work of IP evaluation. Whether it is on the table, or under the table, it’s already happening.
In terms of the maturity of the industry, I’m actually shocked at how slow we are as an industry. Ultimately, there’s money to be had from collaboration and that will drive it. That’s the only hope I see. If I just looked at the cultural and historical [trends with regards to standards], I’d be worried.
Ralph von Vignau: I don’t believe there will be a standards group that evaluates IP. There may be certification groups for those who are willing to have their IP certified. I’ll go that far, but no farther [in predicting the availability of such services]. I agree with Warren – the nature of IP is changing so rapidly!
I’m a person who’s normally optimistic. I see a major change between the standards we used to develop, and making money on those standards. Today the majority of the standards organizations are about opening markets, about making sure people can interoperate. Although, we have yet to fully prove the ROI for doing this, I believe there are standards coming along that are showcasing these opportunities for the industry.
We’re not there yet, but because there’s a heavy investment – one of the arguements about the IEEE – they even understand this now. The electronics industry is a fast-moving, changing, volatile market and you need standardization. We must do this work to survive.
Bill Martin: We work at the leading edge of IP, and I agree with Warren and Ralph. Things are too fast moving to do [formal qualification of IP], but as things get accepted you’ll be able to set up an organization [for certifying IP]. I actually had a talk with a small company about setting up a business to qualify IP – it’s a value proposition [that’s now emerging]. At some time in the future, I believe you’ll see it.
The maturity of the industry? There’s no question that the entire high-tech market continues to evolve. Back 50 years ago, the first transistor was manufactured. Now you can’t touch or use any product today that doesn’t have electronics in it. The systems are more complex, larger, and we’re talking about hundreds of millions of transistors on a chip. We can create it, design it, manufacture it, and get it into customers’ hands. The industry definitely continues to mature as a group, and IP is the next place we’re going to be going.
Peggy Aycinena: On that optimistic note, thanks for being here!
Additonal info …
Ian Mackintosh is Founder and President of the OCP-IP Association, which develops and supports standards for IP core interfaces for plug-and-play SoC design. The OCP standard is now up to Version 2.2.
Victor Berman is CEO of Improv, an IP provider specializing in DSP cores. EETimes’ Richard Goering called Victor an “EDA standards guru” last year when Victor left Cadence to take over at Improv.
Ralph von Vignau is Senior Director of the Innovation and Technology Group at NXP, and President of the SPIRIT Consortium, an organization Ralph helped found in 2006 which develops and supports specifications for meta-data and tool interfaces. SPIRIT’s IP-XACT standard “is currently under review with the IEEE Working Group P1685.”
Bill Martin is General Manager of the IP Division at Mentor Graphics, a company which is an Embedded Systems company at ESC, an IP company at IP/Grenoble, and an EDA company at DAC. Bill is comfortable in all of those venues.
Warren Savage is Founder, President & CEO of IPextreme, a company that provides licensing and market distribution support to third-party IP providers. Warren moderated the panel mentioned earlier at IP07 last December.
SPIRIT ( http://www.spiritconsortium.org)
The SPIRIT Consortium officially incorporated as an open, independent, California non-profit organization in July 2006. It announced an enhanced future roadmap covering topics such as debugging, hardware constraints, documentation, and register-description formats. Steps to create alignments with Si2 and SystemRDL in line with the future scope of The Consortium have also been announced. IP-XACT, The Consortium’s official set of specifications for IP meta-data and tool interfaces, has been released to the public and is currently in review with IEEE Working Group P1685.
IEEE P1685 ( http://www.eda-stds.org/spirit-p1685)
The purpose of this project is to provide a well-defined XML Schema for meta-data that documents the characteristics of Intellectual Property (IP) required for the automation of the configuration and integration of IP blocks; and to define an Application Programming Interface (API) to make this meta-data directly accessible to automation tools.
VSIA ( http://www.vsi.org/) … July 2007
For 11 years, the VSI Alliance was the leading IP Standards body, working with representatives from all segments of the SoC industry, easing the integration and reuse of IP. Since its inception in 1996, the Alliance released more than twenty standards, specifications and technical documents that have been widely adopted by organizations worldwide. After helping the industry sort through SoC, IP and reuse issues, the VSIA has announced plans to close and to move successful products to other industry organizations. This was a very difficult decision, particularly with the worldwide successful adoption of the QIP Metric; the tremendous industry interest in the encryption work under way; and the commercial adoption of our IP Transport specifications by Chip Estimate and Design and Reuse. The VSIA website will remain active and available to continue downloading our standards, specifications and white papers.
OCP-IP ( http://www.ocpip.org/home)
OCP-IP is dedicated to proliferating a common standard for intellectual property (IP) core interfaces, or sockets, that facilitate "plug and play" System-on-Chip (SoC) design. Making complex SoC design more efficient for the widest audience, the industry strongly supports the Open Core Protocol as the universal complete socket standard, regardless of on chip architecture or which processor cores are featured.
Accellera ( http://www.accellera.org/home)
To improve designers' productivity, the electronic design industry needs a methodology based on both worldwide standards and open interfaces. Accellera was formed in 2000 through the unification of Open Verilog International and VHDL International to focus on identifying new standards, development of standards and formats, and to foster the adoption of new methodologies.
Accellera's mission is to drive worldwide development and use of standards required by systems, semiconductor and design tools companies, which enhance a language-based design automation process. Its Board of Directors guides all the operations and activities of the organization and is comprised of representatives from ASIC manufacturers, systems companies and design tool vendors.
OSCI ( http://www.systemc.org/home)
Transaction-level modeling continues to grow in importance for architectural exploration, performance analysis, building virtual platforms for software development and functional verification. The recent release of the OSCI TLM-2 draft 2 standard marks a significant milestone in making interoperable transaction-level modeling a reality. A summary of feedback received from the public review of TLM-2 and plans for the next revision of the standard was featured at events held during the DVCon and DATE Conferences. The TLM-2 draft 2 kit is available under open source license.
Si2 ( http://www.si2.org)
Silicon Integration Initiative (Si2) is an organization of industry-leading companies in the semiconductor, electronic systems and EDA tool industries. We are focused on improving productivity and reducing cost in creating and producing integrated silicon systems. We believe that through collaborative efforts, the industry can achieve higher levels of systems-on-silicon integration while reducing the cost and complexity of integrating future design systems.