IPextreme Announces Availability of Market's First IEEE 1149.7 cJTAG Semiconductor IP Core

For additional information and to view the product brochure please visit: http://www.ip-extreme.com/IP/cJTAG.html

cJTAG IEEE 1149.7 Availability and Pricing

The cJTAG -- IEEE 1149.7 product, available from IPextreme today, includes Verilog source code, integration testbench and tests, documentation and scripts for simulation and synthesis, with support for common EDA tools. cJTAG -- IEEE 1149.7 is available for $75K, list price. For ordering details, please contact your local IPextreme office -- http://www.ip-extreme.com/company/contact.html

IPextreme will be hosting a one-hour webinar in mid-September entitled, cJTAG IEEE 1149.7: The Next Generation in Test and Debug. For more details and information please visit: http://www.ip-extreme.com/webinars/

About IPextreme Inc.

IPextreme packages, delivers and supports famous IP (intellectual property) designed by large semiconductor companies and used by system-on-chip (SoC) designers worldwide. These production-proven IP products serve both broad horizontal markets and specific verticals such as consumer and automotive, and are provided in a process-independent and EDA-neutral format for easy use by the widest range of customers. With a decade of experience in developing, packaging, licensing and supporting IP, IPextreme offers a complete business solution that allows semiconductor companies to strategically leverage their internal IP portfolio and expand overall revenue. The company has offices in Campbell, California; Munich, Germany; and Tokyo, Japan with representatives in China, India, Israel, Korea and Taiwan. For additional information, please visit www.ip-extreme.com.

About IEEE 1149.7

The IEEE 1149.7 standard is currently in draft and is headed for ratification by the IEEE in early 2009.

IPextreme and Core Store are registered trademarks of IPextreme Inc.

All other product or service names are the property of their respective owners. All rights reserved.

Note to editors:

A graphical representation of cJTAG interconnects and board-level topologies are available at: http://www.ip-extreme.com/images/cjtag_diagram.gif

For a slide presentation by Stephen Lau of TI on 1149.7, a complementary superset of the 1149.1 standard, see Squeezing the Power out of Debug and Test Interface (DTI) at: http://www.ip-extreme.com/cjtag_preso.pdf

Keywords:

IEEE 1149.7, cJTAG, IEEE 1149.1, JTAG, compact JTAG, test, debug, test and debug, semiconductor IP, IP core, IEEE 1149.1, SoC, system on chip, IC, integrated circuit, embedded systems, multicore devices, mobile devices, power saving



Contact:

For IPextreme:
IPextreme Inc.
Karen Crannell, 408-540-0096
Email Contact
or
Europe:
Bley PR
Annette Bley, +44 (0) 20 7482 4800
Email Contact
or
North America:
Cayenne Communication
Linda Marchant, 919-451-0776
Email Contact



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