SiP or System-in-Package

What is Cadence’s competitive advantage?
There is one big obvious difference which is Cadence is the only vendor that can provide an integrated chip design, packaging design and PCB design flow. We provide all three parts of that design flow. The second reason is because Cadence has IC design as part of our portfolio, we actually understand the whole need for co-design. In fact we were the first EDA company to introduce the idea of co-design between the IC team and the packaging team. We introduced that with our first SiP solution a couple of years ago. We were also the first to introduce a truly focused solution. We are the only one that supplies you chip design, packaging design and PCB design.

Also, the fact that we have such strong customer portfolio of IC companies, packaging foundries and system companies gives us an advantage of being ahead of where the market is going and where technology is going, so that we can provide solutions faster than anybody else.

Anything else to add?

People ask SoC versus SiP. It is not one or the other. They are complementary. They are time when you want to integrate functionality together a system-on-a-chip but there are also times when you want to add peripheral functionality that may change within a very short period of time like memory. That’s were SiP comes. Often you put a SoC into a SiP to complement the SoC with supporting silicon. It is not an either or proposition.

The top articles over the last two weeks as determined by the number of readers were:

IBM and Mentor Graphics to Develop 22nm Computational Lithography Solution for the Integrated Circuit Industry IBM and Mentor Graphics Corporation announced an agreement to jointly develop and distribute next-generation computational lithography (CL) software solutions to enhance the imaging capability of lithographic systems used in the manufacturing of integrated circuits at the 22 nm node and beyond. The agreement is part of IBM’s computation scaling initiative to create the industry’s first computationally based process for production of 22nm semiconductors, also announced

GateRocket Receives $3M In Venture Financing GateRocket today announced it has completed a $3 million Series-A round of financing led by New Atlantic Ventures, Massachusetts Technology Development Corporation (MTDC), and Long River Ventures. Seed-stage investors and Angel groups also participated to bring the total GateRocket has now raised to $4.5 million.

Fresco Microchip Selects Berkeley Design Automation Analog FastSPICE(TM) and Noise Analysis Option(TM) for Single-Chip Broadcast TV Receiver Berkeley Design Automation tools include Analog FastSPICE circuit simulation, Noise Analysis Option™ device noise analyzer, RF FastSPICE periodic analyzer, and PLL Noise Analyzer™. The company guarantees identical waveforms to the leading "golden" SPICE simulators down to noise floor (typically 0.1% or less) while delivering 5x-10x higher performance and 5x-10x higher capacity. It achieves this by using advanced algorithms and numerical analysis techniques to rapidly solve the full-circuit matrix and the original device equations without any shortcuts that could compromise accuracy.

Liga Systems Opens East Coast Customer Support and Development Office Appointing Dr. Pranav Ashar as Chief Scientist and Team Leader The activities at this location will initially be heavily focused on R&D along field and sales support for our customers in the region. Already, five senior developers plus one Sr. Applications Engineer, all simulation experts, have joined Liga Systems at this location. The East Coast Office is headed up by Dr. Pranav Ashar, who has been appointed as Chief Scientist for Liga Systems.
Dr. Ashar’s role is to guide future technology directions and product development for the company. Prior to joining Liga Systems, during his tenure as Department Head at NEC Labs in Princeton New Jersey, Ashar lead the original team that invented the underlying core technology embodied in Liga’s hybrid simulator, NitroSIM. In addition, Ashar was co-founder and CTO at Netfortis, and CTO at Real Intent.

Other EDA News

Synopsys and Microsoft Work Together to Improve Electronic Design Productivity
Synopsys Adds Incremental Signoff-Quality Design Rule Checking to IC Compiler
Largest ANSYS International Conference To Date Underscores Increasing Value of Engineering Simulation
Numetrics Enhances NMX-ERP Software Suite With Extensive Customization Capability
Inauguration of SoCIP 2008 Seminar & Exhibition Showcasing Advanced SoC design Solutions
MosChip Launches System-on-a-Chip (SoC) Processor for Digital Content Management in Camcorders, DVRs, Blu-Ray Disc Recorders, Video Editors and other AV Storage Devices
Tilera's TILEPro Multicore Processors Set New Performance Benchmark
Cypress Combines PSoC® and Non-Volatile SRAM Technologies for Fail-Safe, Mixed-Signal Data Logging
Cypress Teams with Europractice to Ensure Cost-Effective Availability of Cypress's Solutions to EU Academic Institutions
Cambridge Analog Technologies Deploys Cadence Virtuoso IC 6.1.3 for Faster Tapeout of Low-Power Mixed-Signal Chip
Si2 Announces Release of Common Power Format Version 1.1
Tensilica Presents "Everything You Wanted to Know About Blu-ray Audio - but were afraid to hear"
Mentor Graphics Announces Precision Synthesis Support for New Xilinx Virtex-5 TXT Field Programmable Gate Arrays
Synopsys Announces the Tapeout of NEC Electronics' Latest EMMA System LSI Using IC Compiler
DVD Disc Manufacturer Dicentia Infringing MPEG-2 Patents, German Court Says
Cadence Works With SMIC to Deliver Virtuoso IC 6.1-Enabled Mixed-Signal Reference Flow and Process Design Kit
Intellitech ships new multi-voltage JTAG multiplexer to compete with IEEE 1149.1 linking devices from Texas Instruments and National Semiconductor
ADVISORY/ IPextreme CEO Warren Savage on Expert Panel Discussing IP Ecosystem at GSA IP Conference
Infinisim Announces RASER, Breakthrough Simulator for Mixed-Signal Designs
MOSAID to Hold Annual General Meeting
ISQED'09 Now Accepting Papers & Speakers for the 10th Anniversary Event
Synopsys Enters Mixed-Signal Implementation Market With Galaxy Custom Designer
Domino Logic in ASIC Design Flow - Detailed Methodology and Breakthroughs in High Speed Design Automation Approach
Cadence Virtuoso Platform Enables Custom IC Designers to Achieve Breakthrough Results
TOOL Corp. has Started Selling MS-lite, a Fracturing System for Small and Medium-sized Data
SMIC 2008 Technology Symposium Held in Shanghai
Toumaz Technology CEO Keith Errey to Present Vision for Digital Medicine Future at Oracle OpenWorld 2008
Media Advisory: Cadence Seeks Silicon Valley Beneficiary for 2009 Stars & Strikes Fundraiser
Tanner EDA Provides Customers with Seamless Integration to Mentor's Calibre Verification Suite
Dassault Systemes SolidWorks Corp. Unveils SolidWorks Enterprise PDM 2009
Mentor Graphics and PTC Deliver Industry's First Bi-Directional ECAD-MCAD Collaboration Capability
Solido Design Automation to Showcase Analog/Mixed-Signal Statistical Variation Design Tool at CICC
Agilent Technologies' New Electronic System-Level EDA Platform Helps Algorithm Developers, System Architects Cut Design Time in Half
IBM and Mentor Graphics to Develop 22nm Computational Lithography Solution for the Integrated Circuit Industry
Liga Systems Opens East Coast Customer Support and Development Office Appointing Dr. Pranav Ashar as Chief Scientist and Team Leader
GateRocket Receives $3M In Venture Financing
TILE64 Processor Certified by BDTI as Highest Performance Embedded Processor on OFDM Benchmark, Delivering up to 10x the Performance of High-End DSPs
Tanner EDA Delivers First 64-Bit Physical Verification Tool Suite on Windows (x64) Platform
Fresco Microchip Selects Berkeley Design Automation Analog FastSPICE(TM) and Noise Analysis Option(TM) for Single-Chip Broadcast TV Receiver

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