June 24, 2009 — The HIP 3100 is a high performance SPI flash memory controller IP core. It allows flexible, efficient, and high performance implementation of SPI memory flash subsystem on AHB bus. The SPI controller (HIP 3100) offloads AHB master and software from direct control of data transfers to/from flash memory subsystem, generation of SPI memory control signals, and increases overall memory subsystem performances. Up to 4 parallel and independent data transfers to/from memory subsystem can be executed, increasing overall performances by a factor of 4 or more. With a broad set of configuration registers, control fields, interrupt signals and Tx/Rx FIFOs, the communication between software/AHB master is minimized to the lowest possible level, offloading software and AHB master from direct control of flash memory subsystem and data transfer execution. The flash memory subsystem can be organized in up to 4 memory clusters, each having up to 4 flash memory devices. Each memory cluster has a dedicated set of configuration registers and Tx/Rx FIFO pair.
The main features of the HIP 3100 AHB SPI flash memory controller IP core are:
- -SPI flash memory controller with AHB slave interface
-Decodes and executes SPI flash memory instructions issued by AHB master
-Provides accurate control signals timing on SPI flash memory interface
-Allows efficient data transfers (read/write) between AHB master and SPI flash memories
-Set of configuration registers to control efficient data transfer between AHB master and SPI flash memories and facilitate software control of the SPI controller
-Offloads AHB master from executing data transfer and controlling the SPI flash memories
-Provides the information about the status and outcome of data transfer to AHB master by interrupt mechanism and status register
-Supports hierarchical organization of SPI flash memories:
- -up to 4 SPI flash memory clusters
-up to 4 SPI flash memories in each cluster
-Data transfers can be executed in parallel at SPI memory cluster level providing additional offload level for AHB master
-Dual port Tx/Rx FIFO for each flash memory cluster
The HIP 3100 IP core supports Spansion S25FL032-P/ S25FL064-P and Winbond W25X SPI flash memories. Other models and vendors will be supported soon. The HIP 3100 IP core is suitable for general SPI flash memory subsystem within AHB system, embedded devices with flash memories, solid-state disk (SSD) and any other application having SPI flash memory subsystem.
The HIP 3100 IP core is available now.
If you are interested in finding out more about the HIP 3100 IP core, please visit www.hdl-dh.com or download the datasheet from the following link: http://www.hdl-dh.com/ipproducts.html
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