New Course Offering - STAR Yield Accelerator Class
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New Course Offering - STAR™ Yield Accelerator Class

STAR™ Yield Accelerator
Virage Logic Educational Center
October 14, 2009
9:00am - 5:00pm
Fremont, California


Reservation Deadline:
October 12, 2009
Course Cost:
$1,500 per student

Can’t make the class?
Join us for one of these upcoming dates.


November 10-11, 2009

Virage Logic’s new STAR Yield Accelerator course provides training for optimal utilization of the STAR Memory System’s capabilities, based on the test and diagnostics automation tools available from Virage Logic’s STAR Yield Accelerator software package for manufacturing test. This one-day course features a combination of interactive lectures and hands-on labs that will cover the following topics:

  • STAR Memory System Overview
  • STAR Memory System on-chip structure and basic operations
  • STAR Memory System design verification with STAR Verifier
  • Creating a pattern for memory testing (pass/fail) on ATE
  • STAR Memory System test scheduling mechanisms on the ATE
  • Creating test patterns to implement memory hard and soft repair
  • Patterns to get failing status of an individual memory (DIAGS_SEL)
  • Processing tester log files with Silicon Debugger
  • Understanding comments in WGL and parsing tester data log
  • Pattern for memory isolation (single/group memory testing)
  • Memory characterization flow
  • Understanding and creating patterns to alter TEST1 and RM settings
  • Creating alternative MARCH algorithms
  • Understanding diagnostic flows
  • Creating diagnostic patterns and analyzing results (bitmap)
  • Understanding the Yield analyzer flow
  • Learn how to create and implement the product in SoC designs for lower test costs, improved yield and shorten time-to-manufacture

STAR Yield Accelerator Class
October 14, 2009
Virage Logic Headquarters
Fremont, California
CLICK HERE TO REGISTER

Who Should Attend – New and Existing Users

The STAR Yield Accelerator course requires prior knowledge and moderate experience with the STAR Memory System. The course is intended for design engineers responsible for the generation of the test manufacturing patterns as well as for product engineers responsible for running the test on automatic test equipment (ATE) and performing diagnostics, failure analysis and yield analysis.

Seating is limited so confirm your reservation today!




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