Avery Design Systems Announces SCSI Express (SOP/PQI) Verification IP Solution

ANDOVER, Mass. — (BUSINESS WIRE) — August 22, 2012 — Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of its SCSI-Xactor verification IP targeting SCSI Express for high performance PCIe-based SSDs. SCSI-Xactor extends Avery’s portfolio of storage-related VIP which also includes NVM Express, USB Attached SCSI (UASP), USB Mass Storage Class Bulk-Only Transport (BOT), MIPI Universal Flash Storage (UFS), and SATA.

SCSI-Xactor is based on the standards work of INCITS T10's SOP-PQI Working group and the SCSI Trade Association. The protocol is based on the SCSI over PCIe (SOP) host interface specification which enables SCSI initiators communicating to SCSI targets over PCIe through the PQI transfer layer. This new protocol will enable SCSI devices to utilize the faster PCIe transport required to meet the demand in next generation enterprise designs.

SCSI-Xactor is a complete verification solution for SCSI Express core and system design. SCSI -Xactor allows design and verification engineers to quickly and extensively test the functionality of SCSI Express controller-based designs. The SCSI -Xactor solution includes:

  • SCSI Express host software BFM
  • SCSI Express host and controller bus adaptor
  • Reference SCSI Express controller and adaptor for emulating SCSI targets
  • Producer-consumer scoreboard
  • Compliance testsuite
  • Comprehensive protocol checks
  • Protocol analyzer tracker
  • Functional coverage model
  • Works with any PCIe and AXI IP or VIP

SCSI-Xactor works in conjunction with Avery’s leading PCI-Xactor PCI Express Verification IP solution to supply a complete SCSI Express subsystem verification environment. A SCSI Express bus adaptor layer enables the SCSI Express host software BFM to hook up to any bus interface such as PCIe and AMBA AXI and enables running the SCSI Express host software BFM with or without the PCIe root complex and endpoint IP stacks yielding faster simulation performance for large data movement in both SCSI Express core-level and SOC-level verification environments. A reference SCSI Express controller supports core-level verification by emulating the NAND Flash backend subsystem.

Models and compliance testsuites are developed in SystemVerilog and support UVM, OVM, and VMM environments.

“Avery is focused on delivering industry leading VIP for the rapidly emerging SSD and other storage-related standards built on top of PCIe, USB, and MIPI base protocols,” says Chilai Huang, president of Avery Design Systems. “Our solution enables designers to thoroughly verify their designs functionally adhere to the new SCSI Express standard and effectively pinpoint areas of non-compliance or performance bottlenecks.”

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for automatic property and coverage generation and RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, MIPI, DDR/LPDDR, NVM Express, and SCSI Express standards. The company is a member of the Synopsys SystemVerilog and VMM Catalyst Programs, Mentor Graphics Modelsim Value Added Partnership (VAP) program, and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.



Contact:

Avery Design Systems
Chris Browy, 978-689-7286
Email Contact




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