SUNNYVALE, CA--(Marketwired - May 28, 2014) -
Real Intent, known for having the fastest, highest-capacity verification tools for static functional analysis including Lint, and for advanced RTL sign-off of designs with multiple clock domains (CDC)
Is bringing lots of valuable information and fun to the Design Automation Conference (DAC) 2014 in San Francisco June 2-4, 2014, at Booth #1825:
Technical presentations about its new product releases proven on 500M+ gate SoC designs.
- New Ascent Lint 2014 with blazing speed for debugging - The industry's fastest linter for cleaning RTL now has 46+ new comprehensive rules; it analyzes 500M gates in less than one hour with no need for hierarchical processing, and features debugging with the Emacs editor, hierarchical waiver management, SystemVerilog 2009 support, and new integration with MATLAB® from Mathworks.
- Meridian Clock Domain Crossing with advanced flows and debug features - It offers market-leading speed, capacity and low-noise analysis of asynchronous clock domains in SoC designs, and improves the memory footprint and runtime performance by almost one-third.
- Ascent XV comprehensive static solution for the latest in X-propagation verification, reporting and debug - Its unique ability to seamlessly integrate techniques of simulation, static analysis and formal analysis into a unified flow maximizes coverage and minimizes user burden to achieve X safety. It ensures that simulation performance and accuracy are not impacted by X-effects; it precisely identifies all X-sources and X-sensitive nets, and ranks which nets to analyze first; it identifies uninitialized flops and suggests a minimal number of hardware resets for complete initialization with minimal RTL changes; and it provides initialization and optimization capability for power-managed blocks to ensure that the combination of resets and retention flops establish a known state.
- Ascent IIV: Automatic detection of functional bugs without a test bench - Leveraging formal techniques for functional verification, it uses the implied RTL intent to formulate checks automatically, find elusive bugs in RTL blocks and pinpoint the root cause of the problem. Its smart reporting prioritizes debug effort by marking up to 90-percent of the failures as secondary or duplicate, reducing the time spent on analysis. The new 2014 release minimizes debug time with enhanced root cause analysis, smarter reporting and new FSM checks -- shrinking the debug signoff burden to almost nothing for a very large amount of checks.
Other technical presentations
- How to accelerate RTL sign-off of SoC designs with a best-in-class solution - It covers a full suite of static verification concerns including syntax and semantic checking (lint); constraints planning and management; reset analysis and optimization; automatic intent verification; CDC sign-off; DFT analysis and insertion; and X-analysis and optimism/pessimism correction.
- Joint Meridian CDC and Defacto STAR DFT Flow - First-time showing of a combined RTL sign-off flow for both CDC and DFT that accelerates the sign-off process. The new flow integrates Defacto's STAR DFT evaluation and enhancement platform, and Real Intent's Meridian CDC to offer a best-in-class solution for SoC design teams worldwide.
- Pavilion panel organizer: "The Asymptote of Verification" - Bryon Moyer, editor of EE Journal will moderate the discussion as panelists from Cavium, Infineon Technologies AG and NVIDIA talk about bringing a higher level of automation, predictability, and ROI to system-on-chip (SoC) functional verification, based on their real experiences with formal verification, static RTL analysis and graph-based verification technologies.
- Passport Partner program - Visit Real Intent industry partners Calypto, Defacto and MathWorks that share joint flows with Real Intent, and enter to win several $100 gift cards or a 10-inch Android tablet.
- Verification survey at the booth - Enter drawings for a Pebble Smartwatch, Google Chromecast, or Golden State Warriors tickets.
- Video game - To celebrate the 2014 FIFA World Cup Brazil, come and play as the captain of your country's team.
- Free photo booth - Get an entertaining take-away for you and your colleagues.
- Roses give-away - Come and receive yours as a sweet thank-you gift for our visitors.
Click here to see a very informative five-minute video by Real Intent President & CEO Prakash Narain. In it he references Real Intent's mission to make RTL signoff more efficient and previews four products it will highlight at DAC 2014 that advance the state of the art.
The Design Automation Conference (DAC) is recognized as the premier conference for design and automation of electronic systems. System designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives, and researchers and academicians from leading universities represent the diverse worldwide community of more than 1,000 organizations that attend DAC each year. DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors.
When / Where
Mon. - Wed., June 2-4, 9 a.m. - 6 p.m., Booth #1825
Mon. - Wed., June 2-4, 10 a.m. - 5 p.m., Booth #1825
Mon., June 2, 5:15 - 6 p.m., Booth #313