SUNNYVALE, Calif. and YOKOHAMA, Japan – Sept. 26, 2014 –
Real Intent, whose advanced verification solutions accelerate electronic design sign-off, eliminate complex failures in SoCs, and lead the market in performance, capacity, accuracy and completeness
Will exhibit its Ascent™ and Meridian™ products for accelerating RTL sign-off, at the Design Solution Forum 2014 in Yokohama, Japan next week. Sponsored by the Japan Electronics Show Association, this seminar brings together engineers throughout Japan to share the latest information about design, verification, software and FPGA technology trends. Yasuo Torisawa, Country Manager at Real Intent KK, will help attendees learn more about Real Intent’s Ascent tools – the fastest and highest-capacity verification solutions available for uncovering issues prior to digital simulation – and its Meridian products that accelerate sign-off verification of clock domain crossings and timing constraints in giga-gate SoC designs. These products include:
- Ascent Lint, the industry’s fastest and lowest-noise RTL lint solution.
- Ascent Implied Intent Verification (IIV), an early functional verification tool that automatically finds elusive bugs in RTL to improve verification efficiency substantially, and can detect up to 50-percent of design functional errors prior to testbench development and simulation.
- Ascent X-Verification System (XV), which detects and isolates X-propagation issues early, in Verilog RTL, eliminating costly error-prone debug at the netlist level, and prevents hidden functional bugs from slipping through to silicon.
- Meridian CDC, the fastest, highest capacity and most precise CDC solution in the market and the only solution that enables all aspects of CDC sign-off.
- Meridian Constraints, the best-in-class comprehensive constraint management solution in the market.
Friday, Oct. 3, 2014 (10:00 – 18:00)
Shin-Yokohama Kokusai Hotel
Seminar: Third and fourth floor conference room
Table exhibits: Second floor, Queens Hall
Kohoku-ku, Yokohama, 222-0033 Japan
About Real Intent
Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. Real Intent’s comprehensive CDC verification, advanced RTL analysis and sign-off solutions eliminate complex failure modes of SoCs, and lead the market in performance, capacity, accuracy and completeness. Please visit www.realintent.com for more information.
Real Intent and the Real Intent logo are registered trademarks, and Meridian and Ascent are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.
CDC: Clock Domain Crossing
EDA: Electronic Design Automation
FPGA: Field Programmable Gate Array
RTL: Register Transfer Level
Sarah Miller for Real Intent
ThinkBold Corporate Communications