Real Intent Unveils New Release of Ascent Lint for Early Verification of Digital Designs
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Real Intent Unveils New Release of Ascent Lint for Early Verification of Digital Designs

Enhancements and new features add broader hardware language support, DO-254 compliance testing 

SUNNYVALE, Calif. – Feb. 25, 2015 Real Intent, Inc., whose verification solutions accelerate electronic design sign-off, today announced the latest version of its Ascent Lintproduct with significant new enhancements for users. Real Intent’s Ascent products find design errors leading to improved quality of results and higher productivity for both design and verification engineers.

Ascent Lint already is the industry’s fastest and most accurate tool for early verification of digital designs. The new version for 2015 delivers enhanced support for the SystemVerilog language, DO-254 policy files for compliance testing of complex electronic hardware in airborne systems, deeper rule coverage and easy configurability. Additional notable enhancements and new features for Ascent Lint include:

Ascent Lint is tightly integrated with MathWorks’ HDL Coder™ that automates the setup of files and commands for Ascent Lint. HDL Coder generates portable, synthesizable Verilog® and VHDL code from MATLAB functions, Simulink models, and Stateflow® charts, for users of the MATLAB and Simulink® products. Kiran Kintali, Product Development Lead at The MathWorks, explains the significance:  “This tight integration enables users to verify that the RTL code generated using HDL Coder is compliant with users’ coding conventions and industry standards for a safe and reliable implementation flow for digital synthesis tools used by ASIC and FPGA designers. We see that Ascent Lint has excellent performance and accuracy in verification of our extensive library of toolbox functions. We believe the new DO-254 compliance testing will be a welcome addition for the thousands of users of HDL Coder.”

Many RTL engineers have been proponents of RTL linting since its inception to deliver high-quality functional designs on schedule. These engineers lint their designs constantly to uncover common and uncommon code issues to try to avoid spending expensive cycles in the simulation and synthesis stages. The Ascent Lint flow gives designers a setup-free, push-button process that provides interactive results and can be run at any point in the hierarchy – from chip level to complete blocks to leaf modules. Designers have confidence in the tool because the reporting of false failures is very unlikely.

According to Graham Bell, vice president of Marketing at Real Intent, “Our new Ascent Lint release addresses the needs of companies developing next-generation designs for FPGAs or complex SoCs. It is a direct result of Real Intent experts working with industry leaders to define and implement richer rules. The addition of DO-254 compliance testing helps ensure that designers’ airborne electronics meet the industry standard for quality and reliability. The new enhancements demonstrate Real Intent’s commitment to support design engineering teams with the best possible tools for verification of digital designs.”

For more information about the new enhancements for Ascent Lint, please click here to see a short (two-and-a-half-minute) video by Srinivas Vaidyanathan, staff technical engineer at Real Intent. In addition, Real Intent will exhibit the new version of Ascent Lint, along with its other products, at DVCon, CDNLive Silicon Valley, and SNUG Silicon Valley next month. 


The new release of Ascent Lint is available in March 2015. Pricing depends on product configuration.

About Real Intent
Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. Real Intent’s comprehensive CDC verification, advanced RTL analysis and sign-off solutions eliminate complex failure modes of SoCs, and lead the market in performance, capacity, accuracy and completeness. Please visit for more information.


ASIC:      Application-Specific Integrated Circuit
CDC:      Clock Domain Crossing
EDA:      Electronic Design Automation
FPGA:    Field-Programmable Gate Array
HDL:      Hardware Description Language
RTL:       Register Transfer Level
SoCs:     Systems-on-Chip
VHDL     VHSIC High-level Design Language

Real Intent and the Real Intent logo are registered trademarks, and Ascent, Meridian and iDebug are trademarks of Real Intent, Inc. MathWorks, MATLAB, Simulink and Stateflow are registered trademarks of The MathWorks, Inc. See a list of additional trademarks. All other trademarks and trade names are the property of their respective owners.

Press contact:
Sarah Miller for Real Intent
ThinkBold Corporate Communications
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