Lowering the Barriers to Mixed-abstraction Verification
The complexity of today's SoC verification environments often requires designers to spend valuable time building and verifying multiple and usually incompatible verification models of a single block to support system-level, TLM-level and RTL-level verification. This lack of consistency prevents teams from easily moving up and down in abstraction and maximizing verification effectiveness. Mentor's unique Questa Multi-view Verification Components product can connect to any level of abstraction from system to gates -- ensuring consistent model behavior and giving the verification team more options to improve performance and increase coverage.
Algorithmic Stimulus Generation Gets to Coverage Faster
Once verification components are available, designers need to create the stimulus to drive the models. Creating test stimulus by hand is one of the most time-consuming steps in the verification flow. Using advanced algorithms to synthesize non-repeating stimulus, Mentor's new intelligent testbench automation technology, inFact, simultaneously reduces test creation time, minimizes redundant testing, and stimulates more of the design -- resulting in more bugs found and dramatically faster time to coverage.
Accelerating Adoption of Breakthrough Verification Methods
Combining these new tools with the Questa functional verification platform, the Open Verification Methodology (OVM), and standards like SystemVerilog, Mentor is opening the doors to broader adoption of breakthrough verification flows.
"The next major step in advanced functional verification happens when manual, time-consuming tasks are replaced with new levels of automation and tool intelligence," said Robert Hum, vice president and general manager of Mentor Graphics Design Verification and Test division. "With the Questa functional verification platform, we believe we're on the right track -- not only from a technology point of view, but also in terms of providing a complete, comprehensive solution."
"At SanDisk we performed an exhaustive evaluation of all testbench technologies, including constrained random testing and intelligent testbench automation," said Ed Tuers, former ASIC Engineering Manager at SanDisk Corporation. "The intelligent testbench automation approach allowed us to do significant pioneering work in this area and translated into a much more streamlined, reusable approach to testbench development. Using the inFact tool suite we were able to find bugs missed by a very extensive set of directed simulations."
"The exploding cost of embedded software design puts increased pressure on SoC budgets. Since there is no immediate answer to the software crisis, management is now focused on the high cost of verification," stated Gary Smith, founder and chief analyst for Gary Smith EDA. "Throwing engineers at the problem is not an acceptable answer, whether they be in the US, Europe or India. The target is to bring verification costs down to 35% of the total hardware design cost and we can only do that through automation. The intelligent testbench is the missing ingredient in today's verification flow. At DAC 2007 we saw three start-ups addressing the problem. Today Mentor announces their intelligent testbench tool. Help is on the way."
Pricing and Availability
inFact is available now and Questa MVCs will be available in Q2 2008. Pricing starts at $25,000.
Questa Functional Verification Platform
The Questa functional verification platform combines high-performance and high capacity with the most comprehensive verification capabilities in the industry. Assertion-based Verification (ABV), intelligent testbench automation, Multi-view Verification Components (MVC), and Coverage-driven Verification (CDV) are supported natively by the Questa platform's high-performance assertion engine; a modern, high-performance constraint solver; and extensive functional coverage features, including verification management leveraging the Unified Coverage Database (UCDB). Verification of low power design functionality can be proven in an RTL environment with power-aware functional verification. This full set of advanced verification functionality is enabled by a flexible Open Verification Methodology (OVM) that delivers unrivaled language and feature support in any design and verification flow.
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For more information, please contact: Carole Thurman Mentor Graphics 503.685.4716 Email Contact Suzanne Graham Mentor Graphics 503.685.7789 Email Contact