Calypto Partners with HD Lab to Enable System Level Design Flows in Japan
[ Back ]   [ More News ]   [ Home ]
Calypto Partners with HD Lab to Enable System Level Design Flows in Japan

SHIN-YOKOHAMA, Japan & SANTA CLARA, Calif.—(BUSINESS WIRE)—June 4, 2008— Calypto Design Systems Inc., the leader in sequential analysis technology, has signed a partnership agreement with HD Lab of Shin-Yokohama, Japan, where HD Lab will provide sales, support and services for designers using the Calypto SLEC (Sequential Logic Equivalence Checker) product family.

HD Lab, a well-known technical consulting company specializing in system-level design for the last 11 years and expert in system-level languages, design and verification, will provide electronic system level (ESL) design and methodology services based on SLEC System. Enabling ESL, Calyptos SLEC System is the semiconductor industrys only functional verification solution to formally verify equivalence between ESL models and register transfer level (RTL) implementations.

Japanese electronics companies continue to lead the way in ESL design methods, remarks Eiki Suzuki, president of Calypto Design Systems, K.K. Having the expertise of HD Lab as our partner gives Calypto an additional presence and technical strength in the Japanese market.

Based on Calyptos patented Sequential Analysis Technology, SLEC System finds design errors that other tools miss by comparing functionality of an ESL model written in C/C++/SystemC with its corresponding RTL design or system-level model for all possible input sequences. Unlike combinational equivalence checkers, SLEC System does not require one to one mapping of registers. The quality of verification SLEC System performs in minutes is equal to months of running simulation.

SLEC System provides key capabilities for customers adopting system-level design techniques, says Yoshifumi Nagano HD Labs chief executive officer. We are very delighted to be working with Calypto.

Calypto will offer demonstrations of its advanced power optimization and functional verification software during the 45th Design Automation Conference (DAC) in booth #1354 June 9-12 at the Anaheim Convention Center in Anaheim, Calif. Visitors will learn how PowerPro CG (clock gating) and SLEC enable design teams to dramatically reduce power and improve design quality. To register for a private demonstration, visit

About HD Lab

HD Lab, Inc. was founded in 1996 as a professional solution provider for large-scale digital system design. Since its inception, the company has focused on the hardware description language and electronic system level aspect of large-scale LSI design. Services are provided and delivered in various forms, including consulting services, training and publications. The company is headquartered in Shin-Yokohama, Japan, and serves customers in Japan. More information can be found at:

About Calypto

Founded in 2002, Calypto Design Systems, Inc. empowers designers to create high-quality, low-power electronic systems by providing best-in-class power optimization and functional verification software, based on its patented sequential analysis technology. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program and the Mentor Graphics OpenDoor program. Calypto has offices in Europe, India, Japan and North America. Corporate Headquarters is located at: 2933 Bunker Hill Lane, Suite 202, Santa Clara, Calif. 95054. Telephone: (408) 850-2300. More information can be found at:

Calypto, PowerPro, SLEC and Enabling ESL are trademarks of Calypto Design Systems Inc. Other products and company names may be trademarks or registered trademarks of their respective companies.


Public Relations for Calypto Design Systems
Nanette Collins, 617-437-1822
Email Contact