“The Verification Academy provides well-sized, informative presentations on some of the advanced verification techniques used by Icera, from high-level processes of interest to managers, through to technical material for hands-on engineers,” said Kevin Dewar, Silicon Engineering Director, Icera Semiconductor. “We expect to use the material to develop the skills of engineers new to these techniques, and to refine the skills of experienced engineers.”
About the Verification Academy: Where Education Meets Opportunity
A web seminar to introduce the Verification Academy to prospective users is scheduled for August 12, 2009, 9:00 AM – 10:00 AM (PST). For more information on the seminar visit: http://www.mentor.com/products/fv/events/verification-academy-webseminar.
Currently the Verification Academy contains the following modules with additional modules planned for release over the coming year:
Evolving Capabilities Module
Ensuring functional correctness on RTL designs continues to pose one of the greatest challenges for today's ASIC, FPGA and SoC design teams. This module provides a common framework for all advanced functional verification modules contained within the Verification Academy. A simple evolving capabilities model is presented, which can be used as a tool for assessing an organization's functional verification process capabilities.
Assertion-Based Verification Module
The design effort for complex ASICs has been able to scale linearly by increasing design reuse and adopting a well-architected, platform-based design structure. Unfortunately, functional verification has not benefited directly from this approach. This module explores one way to address increased design complexity to supplement traditional functional verification methods with assertion-based verification (ABV). Today, ABV has been successfully applied at multiple levels of design and verification abstraction —ranging from high-level assertions within transaction-level test benches down to implementation-level assertions synthesized into emulation and hardware.
(CDC) Clock-Domain Crossing Verification Module
For the past dozen or so years, static timing analysis has served the industry well by ensuring that all synchronous design blocks will not violate any of the design’s setup and hold-timing constraints. However, with the convergence of multiple applications into a complex SoC (such as digital-audio, video, wireless, and networking), as well as the industry’s adoption of an IP reuse strategy, project teams are now faced with a new set of clocking verification challenges that are not addressed by static timing analysis. This module introduces clock-domain crossing concepts and provides insight into understanding the challenges encountered in complex SoCs.
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,425 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
(Mentor Graphics is a registered trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)