Lattice ispLEVER Classic Design Tools Now Support New CPLD Family
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Lattice ispLEVER Classic Design Tools Now Support New CPLD Family

                                          – Full Production Support for Ultra Low Power ispMACH 4000ZE CPLDs –

HILLSBORO, OR – AUGUST 25, 2008 – Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of its ispLEVERâ Classic version 1.2 design tool suite. The tool suite supports all Lattice SPLD, CPLD and select FPGA families. Lattice’s ispLEVER Classic tools now provide full production support for the recently released ultra low power ispMACH® 4000ZE CPLD family and also include user-friendly support for several innovative new silicon functions. ispLEVER Classic 1.2 also includes the newest versions of Synopsys’ Synplify synthesis and Aldec’s Active-HDL simulator EDA tools.

“This release of the ispLEVER Classic tool suite offers users immediate access to Lattice’s exciting new PLD technology,” said Chris Fanning, corporate vice president, enterprise solutions. “Our customers will be able to take advantage of the ispMACH 4000ZE’s very low power in a very mature design tool that has been used by many tens of thousands of customers.”

Pricing and Availability

Lattice’s ispLEVER Classic 1.2 for Windows is available now for download from the Lattice website,, without charge. UNIX and Linux versions are available with the full ispLEVER software tool suite. The full ispLEVER design tool suite for Windows is priced beginning at $895.

About ispMACH 4000ZE CPLDs

The ultra low power ispMACH 4000ZE family ranges in density from 32 to 256 macrocells, with exciting new system integration capabilities including an on-chip oscillator and timer, input hysteresis and Lattice’s new Power Guard feature.

Power Guard lowers power consumption by selectively disabling unused input pins so that they do not switch and needlessly consume dynamic power. The on-board oscillator is useful for housekeeping tasks such as “heartbeat” functions, digital de-glitch and control state machines. “Always on” input hysteresis is provided for each pin.

About the Lattice ispLEVER Design Tools

In addition to ispLEVER Classic, Lattice offers the full ispLEVER design tool suite for use with its latest FPGA products. It provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, timing analysis, place and route, in-system logic analysis and more. The ispLEVER tool suite is provided on CD-ROM and DVD for Windows/Vista, UNIX and Linux platforms.

About Lattice Semiconductor

Lattice Semiconductor Corporation provides the industry’s broadest range of Programmable Logic Devices (PLD), including Field Programmable Gate Arrays (FPGA), Complex Programmable Logic Devices (CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products.

Lattice continues to deliver “More of the Best” to its customers with comprehensive solutions for system design, including an unequaled portfolio of high-performance, non-volatile and low-cost FPGAs.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets. For more information, visit

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our third party software suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company’s Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.


Brian Kiernan
Corporate Communications Manager

Lattice Semiconductor Corporation
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