IPextreme Announces Availability of Market's First IEEE 1149.7 cJTAG Semiconductor IP Core

CAMPBELL, Calif.—(BUSINESS WIRE)—September 2, 2008— IPextreme® Inc., the company bringing famous IP (intellectual property) to system-on-chip designers worldwide, today announced the availability of the electronics industrys first synthesizable IP core that implements the upcoming IEEE 1149.7 standard, which will be ratified in early 2009. IEEE 1149.7 will provide designers with powerful extensions to the current IEEE 1149.1 (JTAG) standard, uses fewer pins and maintains compatibility with IEEE 1149.1-based hardware and software. The cJTAG IEEE 1149.7 IP core, provided by IPextreme, is a configurable, ready-to-integrate semiconductor IP solution supporting all six classes of the IEEE 1149.7 standard.

The IEEE 1149.7 test and debug technology will allow the electronics industry to extend IEEE 1149.1 capabilities while also providing increased functionality to their embedded designs, said Stephen Lau, emulation technology product manager, Texas Instruments (TI). IPextreme plays an integral part in enabling rapid adoption of the technology throughout the industry. Their technical expertise and experience in working with semiconductor leaders makes them well-suited for this initiative.

IPextreme continues to play a critical role in providing the industry with leading technology and monetizing semiconductor companies R&D investments, said Warren Savage, CEO & president, IPextreme. Our business proposition allows us to work with a wide variety of technology leaders to produce high quality IP products. Our objective is to make both TI and our customers successful through the adoption of the IEEE 1149.7 standard.

IPextremes cJTAG IEEE 1149.7 Features

IEEE 1149.7 does not change or replace IEEE 1149.1. Instead, it offers a scalable set of extensions to IEEE 1149.1 that ensures interoperability between IEEE 1149.1- and IEEE 1149.7-based devices and test equipment. Features of the cJTAG IEEE 1149.7 IP core include:

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Support for IEEE 1149.7 classes 0-5 (selected through hardware configuration parameter).

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Partitioned along IEEE 1149.7-specified functional boundaries:

-- Extended processing unit (EPU) for class 0-3 operation. Advanced processing unit (APU) for class 4-5 operation.

-- Further parameterization within EPU and APU for class-specific and optional features.
-- Separate blocks for clock and reset signal conditioning.
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Supports all mandatory and optional scan formats: JScan0-3, SScan0-3, OScan0-7 and MScan.

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Supports all mandatory and optional commands.

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Firewall provides robust hot-connection by disabling test clock (TCK) until firewall is disabled by the debug test system (DTS).


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