The Mixel D-PHY is a complete D-PHY IP, optimized for low-power operation and small foot print, and is fully compliant with the MIPI D-PHY specifications. The Mixel MIPI D-PHY is modular, and available in various configurations, up to the recommended four data lanes, each operating at 1 Gbps. The Mixel D-PHY transceiver is fully characterized, available on multiple foundry process nodes, and is in the process of being transferred to production in Mixel customer’s products. Mixel also provides its customers with the Clock Management Unit IP, incorporating a high performance, low jitter PLL and timing circuitry. The Mixel D-PHY and Clock Management Unit ship as GDSII and RTL, with LVS netlist, LEF file, Verilog and timing models, and comprehensive documentation.
“Our partnership with Northwest Logic demonstrates our commitment to providing customers with a best-in-class, total MIPI solution, and furthering our D-PHY leadership position,” said Ashraf Takla, President and CEO of Mixel, Inc. “This solution provides our customers with the best of both worlds. They not only get a proven and co-validated total solution that incorporates both the mixed-signal and digital cores, but they also get best-in-class cores that only expert IP providers like Mixel and Northwest Logic can offer,” he added.
The Northwest Logic MIPI CSI-2 Controller Core implements all three CSI-2 MIPI layers including Pixel to Byte Packing Formats, Low Level Protocol and Lane Management Layer, and is fully compliant with the current version of the MIPI CSI-2 specification. The core supports transmitter or receiver operation, 1-4 data lanes, virtual channels, and all data formats. The core is specifically designed for ease-of-use, including a flexible pixel-based user interface, optional AXI and AHB interfaces, error collection support, and full configurability. The core leverages the full range of Mixel D-PHY features to ensure robust, low power operation. The core is delivered fully integrated with a Mixel D-PHY model along with a comprehensive MIPI verification environment.
“Northwest Logic is excited to partner with Mixel to offer a complete, market-leading MIPI Controller + PHY MIPI Solution. The Northwest Logic Controller Core and Mixel D-PHY have been fully integrated and validated together, to ensure robust MIPI operation. This integration, along with the comprehensive support provided by Northwest Logic and Mixel, ensure that customers can quickly develop, validate, and bring their MIPI products to market,” said Brian Daellenbach, President of Northwest Logic.
The full solution is available for customers to start chip designs today.
Mixel is the leader in mixed-signal mobile IPs and offers wide portfolio of high performance mixed-signal connectivity IP solutions. Mixel’s mixed-signal portfolio includes PHYs and SerDes (suitable for PCI Express, SATA, EPON, XAUI, Fiber Channel, DDR, and LVDS), Mobile PHYs (MIPI D-PHY, M-PHY, and MDDI), general purpose Transceivers, and high performance PLL, DLL IP cores. For more information contact Mixel at Email Contact or visit www.mixel.com .
About Northwest Logic
Northwest Logic, founded in 1995 and located in Beaverton, Oregon, provides high-performance, silicon-proven, easy-to-use IP cores including high-performance Memory Interface Solution (DDR3, DDR2, DDR, Mobile DDR SDRAM; RLDRAM II) and Express Solution (PCI Express 2.0 and 1.1 cores and drivers). These solutions support a full range of platforms including ASICs, Structured ASICs and FPGAs. For additional information, visit www.nwlogic.com or contact Email Contact.