Thanks for the LNV Memory
[ Back ]   [ More News ]   [ Home ]
Thanks for the LNV Memory

Lucky were those who attended a feisty event last October in Silicon Valley entitled:

The LNVM Imperative: What You Must Know!

It not only included breakfast, it also included a smorgasbord of useful info served up by a panel of brainiacks – experts all of them – on the topic of logical nonvolatile memory, LNVM.

If you missed that tasty 3-hour feast, this is the fast-food recap. Appetizers are courtesy of iSuppli's Jordan Selburn. The main course comes by way of eMemory Technology's Charles Hsu, Impinj's Larry Morrell, and Virage Logic's David Sowards. Dessert and coffee are attributable to Sidense Corp.'s Xerxes Wania.

As far as cooking up the answers to the pop quiz at the end, however, you're the Chef du Jour. Get all the answers right, and you'll be ready to attend the DesignCon LNVM panel this week in Santa Clara on January 30th moderated by Dave Bursky.

Bon Appétit!

***********************

Appetizers …

Jordan Selburn is Principal Analyst for Semiconductor Design for iSuppli, and provided opening and closing comments for last October's event, and recapped those comments by phone on January 24th.

Selburn says he's beginning to cover semiconductors from a design perspective, not just looking at the number of new designs, but also what it takes to do a design, plus new functionalities – things like embedded NVM: "This technology is really at a cusp right now, although a cusp can be a broad thing as the people who do embedded DRAM have found out."

Selburn invokes the 3-step Geoffrey Moore Chasm criteria to evaluate historical trends in both the DRAM and SOC markets, and then applies those lessons to predict the LNVM market trajectory:

Per Selburn, "First, you have to have a technology that's doable. For instance, going back ten to twelve years, the concept of a system-on-a-chip became technically possible at .6 micron when the density of the silicon began to allow for a wide range of things on a single chip. That trend also proved itself for DRAM in the 1990's."

"Second, a technology has to be economically viable. SOCs were technically viable at .6 micron, but became economically viable at .5 micron. Embedded DRAM only became economically feasible in the late 1990's, as companies like NEC and Toshiba figured out how to use processes which were primarily logic-based, without sacrificing DRAM density and performance."

"Finally, there's the issue of application demand. Just because you can put ice cream on a hamburger, it doesn’t mean there will be a demand. For quite a while now, SOCs have met all three criteria – technically viable, economically feasible, plus demand – and are now mainstream to the point that I don't even distinguish between SOC and ASIC revenues. So far, however, although embedded DRAM has met [Chasm] criteria 1 and 2, both technically and economically viable, outside of a niche market there have been few demands for the technology … because standalone DRAM has evolved sufficiently to meet performance demands."

Hence, Selburn asks, "Where does this leave us for embedded NVM? Technically we've been able to do it for quite a while, and from a cost perspective there are a number of companies doing LNVM in pure, straight CMOS. So both [Chasm] criteria 1 and 2 have been met – technical and economical viability. But are there applications for LNVM which are more realistic than ice cream on hamburgers? My expectation is yes. We're seeing a whole new set of demands today."

"For instance, there's a big driver from security. That includes both homeland security, where you're encrypting things and want to have hard-wired keys on a chip, and security in terms of digital rights, where you might be broadcasting variable content over the airways and want to make sure that only those with rights to listen to your music or watch your videos can do so. Both homeland security and digital rights technologies are benefiting from embedded nonvolatile memory."

"Plus, there's another application area in chip serialization, which you can't really do in a practical way without some sort of embedded NVM. [It's true], there are some workarounds, but they're not really feasible. However, if you can put some number of bits onto a chip, all of a sudden you've got a capability which ties into RFID. RFID isn't useful if it just says there's something there, but with serialization you can say something's there and what that something is."

"So we're seeing the third [Chasm criteria] piece of the puzzle come into play. Embedded NVM is technically and economically feasible, and now we're starting to see a significant ramp-up in application demands for the technology."

***********************

Main Course …

Charles Hsu is President of eMemory Technology, Larry Morrell is Vice President of IP Products at Impinj, and David Sowards is Vice President of NVM Products at Virage Logic.

These three, along with Kilopass VP Charles Ng and TSMC Senior Director Kurt Wolf, constituted the panel at the October LNVM event in Silicon Valley.

Charles Hsu, Larry Morrell, and David Sowards [with Pat Laserre, Director of Marketing at Virage] submitted answers to the following questions by e-mail. Pay close attention, because you will be tested later.

1) In 30 words or less, please define LNVM.

Charles Hsu – Nonvolatile memory fabricated using a CMOS logic process.

Larry Morrell – Embedded nonvolatile memory that is manufactured in a standard logic CMOS process with no additional processing steps or mask layers in the wafer manufacturing process.

David Sowards – Logic nonvolatile memory is embedded nonvolatile memory which can be manufactured on a standard CMOS logic process and does not require any additional masks, process modifications, or process tweaks.

2) What is "traditional" NVM versus "non-traditional" NVM?

Charles Hsu – Traditional NVM usually means that the NVM cell is fabricated using at least a 2-poly process, while non-traditional NVM means that the NVM is fabricated using a single-poly process.

Larry Morrell – In a traditional NVM, the wafer manufacturing process is customized, at additional cost, to accommodate memory cells with the smallest possible area to maximize density. A large percentage of NVM needs do not require large bit counts, so the smaller sizes are not the most important consideration – overall cost is. In non-traditional NVM the designer can use a lower-cost wafer manufacturing process and save up to 30% on per-wafer charges. If the bit count is small, all this savings is passed on to the chip level.

David Sowards – “Traditional NVM” encompasses a large number of technologies. It includes any type of storage element that retains the "data state" when power is off. This includes ROM, EPROM, EEPROM, Flash, NovRAM. All of these which allow "reprogramability", (excludes mask ROM), have traditionally required additional process masks and steps in order to create an element to store the charge. Traditional storage elements have been floating gate, MNOS, and Ferro-electric. “Non-traditional NVM” would be anything outside these traditional offerings.

3) What are the criteria for choosing LNVM versus embedded Flash?

Charles Hsu – LNVM usually has a larger cell size, but a relatively much simpler process than traditional embedded Flash. Therefore, if the product requires small density and low endurance, LNVM is a much better choice for faster time to market, lower cost, and higher yield.

Larry Morrell – The most important criterion is overall cost. A Flash process will cost at least 30% more to manufacture the wafer over standard logic NVM. But the designer needs to remember that the cost will be born for the entire chip, not just the part of the chip that is memory. So the larger the chip, the higher the Flash premium (at the chip cost level). However, if the design requires a large bit count and tens of thousands of cycles over the life of the product, Flash is ideal.

The second criterion is availability of the Flash process. Flash requires additional development time for the additional manufacturing steps and so lags the standard logic processes by at least 2 generations. Flash has only recently become broadly available in 0.18 um, while advanced digital designs are now done routinely in 90 nm – two generations more advanced.

David Sowards – In general, the main criteria are density of the memory required along with cost. If large amounts of NVM are required, in the 1Mb or greater range, then embedded Flash is typically chosen. For smaller amounts of memory in the 64Kb-or-less range, embedded Flash would be cost prohibitive since there is a significant adder to the wafer cost for the additional masks. Thus LNVM is the better choice there. An additional consideration is the relative amount of NVM to the entire SOC. For the particular LNVM type of technology, a multitude of factors should be considered. But for the greatest risk reduction, one should choose a technology which has been proven to be as reliable as any traditional NVM technologies.

4) Please explain how various metrics play into the argument for LNVM?

Charles Hsu –

* Robustness (with respect to temp, radiation, trauma, stress) – Same and better than embedded Flash due to process simplicity.

* Retention – Same and better than embedded Flash due to lower endurance application

* Cost – Much lower than embedded Flash due to 7-to-9 masking layers less.

* Performance – Better than embedded Flash, because lower power and higher speed are achievable.

* Security –
OTP has better security than embedded Flash.

* Test –
Same or less cost due to the reduced testing time.

Larry Morrell – There are many different types of logic NVM, so the answers are varied. Flash is multi-time programmable (MTP) and uses a floating-gate approach to store charge to determine a memory state. Some logic NVM technologies use the same approach – storing charge on a floating gate – and so would have very similar technical characteristics to Flash relative to retention, temperature, radiation and voltage stress.

Other technologies are one-time programmable (OTP) and use either a fuse or anti-fuse approach. In the fuse approach, a circuit element is damaged on purpose to create an open circuit. This can be done electrically by putting more current through a conductor (i.e., a poly line) than it can handle and thermally destroying the conductor. Other techniques involve cutting metal lines with a laser after the wafer is manufactured, but before it is packaged.

The anti-fuse uses the approach of creating a short circuit. This is typically done by applying a high voltage across a gate and deliberately breaking down the gate oxide.

Both fuse and anti-fuse have the attribute of making physical changes in the device which are hard to validate at the time of the event. Since some annealing can occur at high temperature operation, this could cause “repairs.” That is, the “blown” poly has a property where current can flow through a fuse that wasn’t completely destroyed and in the case of anti-fuse, soft breakdowns can be mistaken for hard breakdowns and could behave differently over operating temperature. Because of the reliability issues with these technologies, some users apply a voting technique, where three fuses are used and they “vote” on the state of the bit. This error correction works for most applications.

David Sowards –

* Robustness (w.r.t. temp, radiation, trauma, stress) – This is, of course, driven by the end application. For those applications that require high reliability under stress, then a technology like NOVeA is an excellent choice because of its proven floating gate reliability over many years of production.

* Retention – Any particular LNVM technology should be able to support the same 10-year data retention as Flash

* Cost – As stated above, LNVM is more cost effective for relatively small amounts of NVM (< 64Kb).

* Performance – Since LNVM is an embedded solution, it allows for high performance due to the fact that you do not have package parasitics such as inductance and capacitance that exist with a discrete solution.

* Security – Since LNVM is embedded in the SOC, it is a much more secure solution than discrete approaches such as EEPROM. With a discrete approach, the data is exposed as it crosses pin boundaries between the NVM and the controller and thus it becomes a security risk. With LNVM the data is embedded and does not cross pin boundaries, which allows for a much more secure solution.

* Test – If a multi-time programmable LNVM is chosen, then you get the benefit of 100 percent verification at test. This is important in that it greatly reduces the likelihood of field failures. If a one-time programmable option is chosen then you do not know if the memory has weak cells and you can get field failures which are very expensive.

5) Please briefly articulate the advantages/disadvantages of one-time versus multi-time programmable LNVM (OTP versus MTP).

Charles Hsu – OTP has 1) smaller size, 2) less IP area, 3) better retention, 4) fast development cycles, 5) lower cost, and 6) higher data. Of course, the disadvantage is that OTP can only be written once.

Larry Morrell – This is mostly an application-specific question. If the use of the product requires a potential for frequent changes to the memory, then multi-time programming is needed. Also, if the user’s reliability requirement necessitates 100% testing of the bits to be programmed, usually multi-time programming is needed even if the end application doesn’t require frequent changes to the data. On the plus side for OTP, it is usually smaller than MTP since it doesn’t have all the erase/rewrite circuitry on board.

David Sowards – For applications that truly require only one-time programmable and require larger amounts of memory, in the 1Mb range, one-time programmable will generally be more cost effective. One drawback of OTP is that it can not be tested. If the memory is shipped to the end application unprogrammed there is no way to test the memory if it is OTP. With MTP, however, you could test it prior to shipping to the end application and thus you know you have a good memory.

MTP can be used in a greater number of security applications because of the fact that it can be reprogrammed. In the event that somebody gets to the encryption key that may be stored in the NVM, you can reprogram the key and thus you are no longer exposed. With OTP you can not reprogram it and thus if a hacker gets the key, the system is no longer secure. A greater number of security and digital rights management applications are turning to MTP for this reason.

6) What is the average data retention today for an LNVM product? Should we expect that to improve over the next several years?

Charles Hsu – More than 10 years, which is satisfactory for consumer electronics applications.

Larry Morrell – Current technology allows for OTP and MTP to be specified from 10-to-50 years for nominal data retention. These figures are based on life testing which, in some cases, takes years to collect. The technology currently deployed may well have longer retention, but there just haven’t been enough years of retention testing performed to make that claim. So the specs may change in the future as more data becomes available.

David Sowards – The average data retention for an LNVM product today is 10 years, which has been an industry standard for quite some time.

7) What process technologies are currently available for LNVM? Which fabs are involved?

Charles Hsu – Process technologies include 0.5 um, 0.35 um, 0.25 um, 0.18 um, and 0.13 um. Fabs include TSMC, UMC, Chartered, VIS, SMIC, Grace, PSC, Siltera, and Winbond.

Larry Morrell – All major foundries are offering some form of OTP or MTP logic NVM. Impinj currently supports TSMC (0.25 um, 0.18 um, 0.13 um, and 90 nm), UMC (0.18 um), Tower (0.13 um). More qualification work is underway with Chartered (90 nm) and with more advanced process nodes at both TSMC and UMC.

David Sowards – LNVM is on a standard CMOS logic process and thus all the major fabs are involved. Nodes from 180 nm through 90 nm are currently available.

8) The LVNM manufacturing process requires high temps. Does this impact yield?

Charles Hsu – In eMemory's Logic NVM, no additional high-temp process is needed.

Larry Morrell – LNVM uses the standard logic CMOS processing steps. The high temperature used in the wafer manufacturing process is part of the normal processing and does not adversely affect the NVM. Impinj sees yields on par with other logic circuits of similar size. Typically yields are in the very high 90’s, percentage-wise.

David Sowards – Only in so much as standard digital CMOS requires high temps. NOVeA does not require any difference in temperature, process, masking, etc., compared to standard CMOS. As such there is no difference in NOVeA yield when compared to standard CMOS.

9) How does the growing RFID market fit into the emerging LNVM market?

Charles Hsu – RFID usually requires 1) low density, and 2) low cost. LNVM is an excellent candidate for RFID.

Larry Morrell – One of the key requirements for RFID is inexpensive re-writeable memory. All RFID chips will need this sort of memory, and since the bit count is not particularly large (a few hundred bits) LVNM is ideally suited for this application.

David Sowards – The growing RFID market is an excellent fit for LNVM. RFID requires a relatively small amount of memory, typically < 2Kb, low cost, and low power. Since LNVM can be manufactured on a standard logic process it is very cost effective and many of today’s LNVM designs are architected to provide extremely low power.

10) Can you rank in order of importance 3 or 4 other applications for LNVM?

Charles Hsu – 1) RFID; 2) MCU; 3) SOC; and 4) smart power management.

Larry Morrell – In terms of driving wafer volume, the important applications are power management, LCD display drivers, digital rights management, RF (not just RFID), and small microcontrollers for consumer applications.

David Sowards – Security and digital rights management for DVD recorders/players, set-top boxes and Flash memory controllers. ZigBee is another strong application for LNVM.

11) Statistics quoted at the October 12th panel suggested the current LNVM market stands at $75 million, predicted to grow to $100 million in 2009. Are these numbers accurate?

Charles Hsu – The numbers are not correct. eMemory alone has more than $100M USD wafer use in its LNVM in 2006.

Larry Morrell – Impinj showed a different view – replacing off-chip EE parts that are less than 4kbits in size results in a market of $300M - $400M currently. Once applications (i.e., RFID, DRM) begin to ship that aren’t yet shipping in large volume, the numbers will be much larger.

David Sowards – From our perspective, yes they are accurate.

12) If the numbers are correct, is this market still too small to generate intense interest?

Charles Hsu – Many markets exist for LNVM including MCU, RFID, analog, PMIC, and so forth. The penetration rate depends on the robustness of LNVM technology.

Larry Morrell – See above. Also, as indicated that (at last count) there are at least 10 companies now offering some form of logic NVM, many are seeing this as a good opportunity. Companies that we know of are:

  • Impinj
  • Virage Logic
  • eMemory
  • Kilopass
  • Sidense
  • Novocell
  • NSCore
  • Jet City Electronics
  • Cavendish
  • TSMC

    David Sowards – Creating a stable and robust LNVM requires a significant investment, thus I do not foresee a lot of other vendors trying to enter this space.

    13) Compare/contrast the LNVM business model to an IP business model.

    Charles Hsu – The LNVM business model can be the same as IP business model, which includes licensing, royalty, and design services.

    Larry Morrell – Most vendors are following the usual IP business model – i.e., licensing fee plus royalties. In some instances, the royalty is paid to the IP supplier by the chip customer and in some cases the wafer manufacturer pays the IP supplier and rolls the costs into the wafer price. License fees vary from as low as $30k for OTP to over $200k for some MTP blocks, and royalties vary from none (where the chip customer pays nothing, the foundry supplies the technology) to 3% or higher.

    David Sowards – The LNVM business is part of the IP business model.

    14) What would a typical LNVM patent describe? The manufacturing process? Materials? Other?

    Charles Hsu – Currently, all the LNVM vendors provide the proprietary patented LNVM "cell structure."

    Larry Morrell – Since LVM is based on *NOT* modifying the logic process, most of the patents are around two areas: 1) Getting the device programmed, or 2) Managing the high voltages necessary to write the data.

    In the case of 1), there are patents in the OTP space describing how oxide breakdowns occur and can be carefully managed with proper high voltage pulses. In the case of MTP, the patents are around the phenomenon of hot-electron injection and Fowler-Nordhiem tunneling. Both of these phenomena have been described previously, but their application in storing charge in a logic process is somewhat new.

    In the second case, managing the high voltage, there are patents in the way high-voltage devices can be constructed in a 3-Volt logic process and how a high-voltage switch can be built using these sorts of devices.

    David Sowards – This will depend on the LNVM technology it is trying to address. For NOVeA, we do not allow any changes to the manufacturing process. As such our patents would not include anything on manufacturing processes or materials. Other LNVM technologies might. Ours would mainly include implementation techniques which allow our LNVM to be implemented in standard CMOS processes.

    15) What are the top 3 things the readers should know about LNVM?

    Charles Hsu –

    1) LNVM is becoming ubiquitous due to its value added as nonvolatile memory, switch/ e-Fuse, and variable resistors.

    2) LNVM enables the low-cost embedded system IC.

    3) LNVM improves the yield and quality of analog and/or mixed-mode ICs.

    Larry Morrell –

    1) It is catching on really, really fast. If your design isn’t taking advantage of this feature, beware – your competition is likely already using it.

    2) Select an IP partner to work with who has a good track record and can help you learn about the technologies and the technical issues to watch out for. There are design considerations that can effect your success. If you know about them early in the architecture of your chip, you may save yourself pain later on.

    3) Select a foundry that has experience in logic NVM. Some foundries understand the technology better than others.

    David Sowards –

    1) It should not require any additional masks or process steps.

    2) It is more cost effective than embedded Flash for densities below 64Kb.

    3) It should be just as robust as Flash; 10-year data retention and 100,000-cycle endurance.

    16) What do readers interested in EDA need to pay particular attention to with regards to LNVM?

    Charles Hsu – EDA facilitates the more efficient and precise design for the IC designer. By using LNVM as 1) code storage, 2) reconfigurable switch, and 3) trimming element/ eFuse, it is indispensable for IC designers who want to achieve highly efficient and precision product design. LNVM becomes a tool to achieve better design. This should be particularly interesting to EDA readers.

    Larry Morrell – LNVM is typically delivered as hard IP. Customers should have a flow that is friendly to incorporating hard IP and have a process that vets the IP vendors both from a tools standpoint and from an NVM experience standpoint. Then everyone wins!


    ***********************


  • Dessert & Coffee …


    Xerxes Wania is President & CEO at Sidense Corp. We spoke by phone on December 15, 2006. Xerxes told me his principal competitors are Kilopass, eMemory, Virage, and Impinj, and he responded to the following questions:

    Q – Will NVM replace logic as the revenue driver for the semiconductor industry in the upcoming years?

    Xerxes Wania – This is a tough question. I don't think that it's going to happen for a few years. Logic will still prevail over memory as such, but lately we have seen more inquiries for large memory blocks. Our LNVM replaces Flash and mask ROM, which is widely used in today's consumer electronic systems and chips. So, in the next 5 years or so, I can see the memory market catching up to logic.

    Q – What are the principal technical hurdles to even denser NVM at this point?

    Xerxes Wania –
    In my 18 years of experience in semiconductors, the biggest driver has been cost from the consumer electronics side of things. However, what's basically stopping the large chips and deployment are the technical hurdles, which are huge.

    There isn't a true NVM solution to replace embedded Flash in standard CMOS processes. The industry is still using .18 micron for Flash, while LNVM has gone down to 65 nm. Flash has not scaled down because technically it has been impossible to do. Instead, people have looked to new technologies – anything from MEMS to MRAM or proprietary technologies. The problem is that these solutions are foundry specific. But when you develop a new technology that's so linked to the foundries, it's hard to go mainstream and blast the world with it. It's not like logic, which you can port to different foundries and scale.

    So the one thing we do have is LNVM, which is in standard CMOS. It is secure, low cost, very dense and faster than Flash which takes care of most of the consumer electronic chips needs.


    Q – Will novel technologies be needed to make NVM competitive with more traditional memory technologies?

    Xerxes Wania –
    Absolutely, but again it's going to be cost driven, and any changes to the standard CMOS process will not be well received.

    Q – How do you rank the various metrics used to characterize an NVM product?

    Xerxes Wania –

    Number 1 is cost.

    Number 2 is reliability. When we started, this was the number 1 concern as it was a new technology, now it has dropped to number 2, and soon it will not be a concern on the list.


    Number 3 is robustness with respect to temperature and stress. Our technology covers the automotive range and is extremely robust.

    Number 4 is retention. In some other solutions, NVM memory can become suddenly volatile. Sidense's memory has retention of over 50 years.



    Number 5 is security. This is not obvious, but a lot of companies are looking at having secure NVM. Customers don't want their systems to be reverse engineered, people revealing security keys, and hackers trying to figure out the embedded code. There are so many ways to break through [the security], that the solution to security will have to include a combination of hardware and software. Our solution is validated by third parties and is extremely secure.

    Number 6 is performance. Today this is a given. If you build something with less performance than Flash, nobody is going to talk to you. If you can't get performance [with your memory], then forget it.

    Number 7 is test. It's now a given, as well, that it's going to be testable and will go through the various test cycles.

     


    ***********************

    Pop Quiz …

    1) True or False: LNVM = Embedded NVM

    2) True or False: LNVM is manufactured in standard CMOS.

    3) True or False: Non-traditional NVM is more costly than traditional NVM.

    4) True or False: LNVM is a traditional NVM.

    5) True or False: Flash memory is better for a design requiring a large bit count than LNVM.

    6) True or False: Flash is a form of NVM.

    7) True or False: OTP LNVM is smaller than MTP LNVM, and therefore easier to test.

    8) True or False: Industry standard memory retention for consumer electronics is 15 years.

    9) True or False: LNVM yield is markedly different from CMOS yield.

    10) True or False: A "voting" quorum for the state of a bit requires 6 fuses.

    11) True or False: An encryption key can be reprogrammed.

    12) True or False: Because it is IP, the LNVM business model does not include design services.

    13) True or False: The LNVM market is expected to top $1 billion in 2008.

    14) Which is true:
    a) RFID usually requires 1) high density, and 2) low cost.
    b) RFID usually requires 1) low density, and 2) high cost.
    c) RFID usually requires 1) low density, and 2) low cost.

    15) An LNVM patent describes:
    a) cell structure
    b) programming the device
    c) managing high voltages
    d) CMOS implementation

    16) True or False: Moore's Law states that technical and economic viability precede an applications market by 18 months.

    ***********************
    Answers …

    T, T, F, F, T, T, F, F, F, F, T-MTP/F -OTP, F, F, c, all apply, not per Gordon.

    ***********************
    Peggy Aycinena is Editor of EDA Confidential and a Contributing Editor to EDA Weekly.


    Rating:
    Reviews:
    For more discussions, follow this link …