Computational Lithography


Lithography tools have long since been pushed past the point where the minimum feature size of the circuits is smaller than the wavelength of light that can be projected through the mask to create them (see well known figure below). In other words, feature-size scaling has advanced faster than the rate of wavelength scaling.

Lithographers have come with several ingenious techniques to address this challenge. The challenges get greater as the industry moves to even lower process nodes.

On September 17th Mentor Graphics announced an agreement to jointly develop and distribute next-generation computational lithography (CL) software solutions to enhance the imaging capability of lithographic systems used in the manufacturing of integrated circuits at the 22nm node and beyond. The agreement is part of IBM’s computation scaling initiative to create the industry’s first computationally-based process for production of 22nm semiconductors.

I had an opportunity recently to discuss this subject with John Sturdevant, Mentor’s Director of RET Support.

Would you provide us with a brief biography?
I manage the technical support organization for our RET product which means we are working both with our leading edge customers to align our product development road map with their RET needs as well as with our engineering groups to in fact specify those new solutions. Our team is heavily involved with 32 nm and 22 nm development around the globe. I’ve been doing that for 5 years. My background prior to that was in lithography R&D. A lithography background is what most of the team of 20 or so people have. It serves us well in this sort of endeavor.

How and when did you arrive at Mentor Graphics?
I started out at IBM for several years in their lithography R&D. I spent 7 or 8 years at Motorola doing the same thing. Then I was manager of lithography R&D at Integrated Device Technology for about 4 years and then came over to Mentor in 2003.

Before we get into the recently announced relationship with IBM, would you describe the general problem as people go from process node to process node as it relates to lithography?
Given my background I probably have a bias as do many fellow lithographers, to see lithography at the center of the semiconductor development universe. It may be only partly true. We have grown accustom to lithography being the gating item for each new technology node. It is certainly true, when you look at the cost of development, particularly the cost of semiconductor equipment associated with lithography. Lithography has typically been gating for each technology node going back well beyond 180 nm. I started at 500 nm. Progress has typically been gated by the ability of the industry to get either new resolution from a lower exposure wavelength or a higher numerical aperture or some combination of those or some other enabling technology to lower the K1. You can chart that all the way back to even one micron days. The interesting thing now, as we look at 22nm development, is that it is the first time in the industry’s history where we don’t have access to a lower wavelength or a higher numerical aperture. Certainly great work continues to go on at 13.1nm for EUV (Extreme Ultraviolet, a politically correct way of saying x-ray lithography). But it is pretty clear that EUV will not be a manufacturable, cost effective solution that will be ready for 22nm. While the numerical aperture has increased up to 1.35 today, which is quire remarkable given what we thought 4 or 5 years ago, it is clear that the fundamental materials limit on the resist, immersion fluid and the optics will limit that. I believe that all three major scanner suppliers have officially jettisoned their plans for research into higher NA. That leaves us going from 32nm to 22nm with exactly the same wavelength and exactly the same NA. So it poses real challenges and that serves as an entrée for IBM and Mentor to collaborate on new approaches to eek out incremental process window at 22nm.

You referenced K1. Would you explain what K1 is?
It is really a sort of fudge factor for the degree of difficulty of the patterning process. It relates to an old equation from Lord Raleigh, which was actually related to astronomy and imaging stars with basic optics. It basically states that the minimum resolution that is achievable is equal to the wavelength divided by the numerical aperture times this fudge factor. If we consider the wavelength and the NA to be fixed, then to get lower resolution, smaller dimensions, we have to lower that K1. Historically it has been a figure of merit or difficulty. In the old days, we would say that a process would only be manufacturable, could yield semiconductor manufacturing, if the K1 is above say 0.7. Well, many, many enablers throughout the value chain in lithography have now put it such that the industry believes that we can achieve it for a K1 at even .3 or .35. The lower the number, the harder it is.

You said that EUV lithography would not be applicable at 22nm.
I believe that is the industry consensus. There was an EUV symposium last week, where industry researchers and experts got together. There is an awful lot of money and momentum behind EUV research but given that some of the fundamental challenges with throughput, how many wafers per hour an EUV scanner could do in manufacturing is down around 2 or 3 per hour, and given price tags of upwards of $80 million for an EUV scanner, I think the industry consensus is that 22 nm will have to be manufactured with existing 193nm wavelength and that EUV will probably be delayed to the next generation, maybe 16nm.

Would you give us an overview of some of RET techniques that have been in use for some time?
On the whole these RET technologies, which I will walk you through, have been things that effectively enable the fudge factor K1 to go down. One of the first ones used in the industry is something called off-axis illumination. It is just engineering the illumination source shape in a pretty crudimentary way so that instead of the light impinging upon the mask in a straight linear fashion, light is brought in off-axis. This goes all the way back to 250 nm days. It was found that by doing this, you could engineer the way light is diffracted off the mask pattern and collected by the imaging optics and that you could get enhanced process latitude. Since then, that has become more and more complex. I will talk a bit later about the technology we are working with IBM, which is a much further extension of the same off-axis illumination approach.

The second technique was phase shift masking (PSM). There are several different types or flavors of PSM. One that has been ubiquitous in the industry at least going back to 90 nm is attenuated PSM technology, which has become quite commonplace and mainstream for many layers. It is referred to as a sort of weak PS (Phase Shifting). It is fairly easy to implement in manufacturing. There is a stronger version of PSM called alternating PSM. That is quite a bit more difficult to manufacture the mask both on the production side of the mask and on the design side of that data. As such, alternating PSM has had spurts and stops by various research groups and a little bit of manufacturing implementation around the world. It has certainly not become mainstream.

Then there is the whole suite of optical proximity corrections (OPC), which have been around probably since 180nm. Certainly our Calibre RET product is involved with supporting all those things. One of the simplest approaches is something called subresolution assist feature, commonly known as SRAF. This is a way to add shapes to the design that do not print on the wafer, yet engineer the diffracted pattern of light to improve the process window. This SRAF technique is very common place. OPC is correcting or biasing the mask to sort of predistort it so that what ends up on the wafer is what the designer wanted. That’s more and more important as that K1 factor goes down. I think overall that the RET techniques have been off-axis illumination, phase shift masking and optical proximity correction (OPC).

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