Avery Design Systems Targets Accelerator Applications With Verification Solutions for CCIX, AMBA 5 CHI, and PCIe 4.0

TEWKSBURY, Mass. — (BUSINESS WIRE) — June 6, 2017 — Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of several new verification IP solutions including the Cache Coherent Interconnect for Accelerators (CCIX), an open chip-to-chip interconnect standard, major updates to the company’s flagship PCI Express® (PCIe®) 4.0 VIP for CCIX over PCIe and PCI-SIG® v0.9 snapshot draft specification, and ARM® AMBA® 5 CHI (Coherent Hub Interface), an on-chip interface specification, that together advance the promise of a new class of accelerator applications connecting processor architectures and accelerators seamlessly through coherent interconnect technologies using the right combination of general-purpose processors and heterogenous acceleration devices such as FPGAs, GPUs, network/storage adapters, intelligent networks and custom ASICs for high performance computing applications.

The CCIX VIP consists of CCIX home agent model incorporating configurable number of request and slave agents, interconnect, and directory agents, protocol checking, snoop response verification, performance measures, and functional coverage. Cache state tracker and transaction-level protocol trackers improve debug. CCIX VIP works in conjunction with Avery’s PCIe 4.0 VIP which has been extended for CCIX transport layer features including the 25GT/s speed. CCIX VIP also supports a transaction layer interface and CCIX-CCIX and CCIX-CHI bridging enabling unit-level verification by bypassing the PCIe layers.

The PCIe 4.0 VIP supports the latest new features including 16 GT/s speed, run time lane margining at receiver during L0, link TX equalization enhancements, PIPE 4.4.1 L1 PM substates, retimer, tag and flow control scaling. Enhancements to protocol tracker logs, protocol checks, and compliance testsuite improve debug and address head-on the verification challenges associated developing Gen4 designs.

The CHI VIP consists of configurable number of request and slave agents, interconnect, and directory agents, protocol checking, performance measures, and functional coverage. A passive monitor performs snoop response verification. Cache state trackers and transaction-level protocol trackers improve debug.

A shared cache coherency verification testsuite for CCIX and CHI is also supported to verify cache coherency and cache state transitions for singular or heterogeneous environments. Test sequences program request and home agent models and cache line states to verify real interconnect, master, and slave designs respond correctly.

“Xilinx has been in close collaboration with Avery to deliver the industry’s first PCIe Gen4 IP and we’ve now expanded the co-development to include CCIX,” said Ravi Sunkavalli, Vice President, IP Design Solutions at Xilinx. “CCIX over PCIe transport comprised of PCIe 4.0 and CCIX transaction, data link, and PHY layer extensions provides the foundation for a high-performance CCIX FPGA accelerator system interface.”

“CCIX enables a new class of interconnect for emerging acceleration applications in the datacenter,” said Gaurav Singh, chairman of the CCIX Consortium. “We are pleased to see Avery taking a leading role in providing early access to IP products to accelerate CCIX adoption among our member companies.”

“Avery is a leader in PCIe VIP and with the emergence of PCIe 4.0 and CCIX enable an entirely new class of FPGA acceleration solutions for datacenter applications in areas of machine learning, network processing, storage off-load, in-memory data base and 4G/5G wireless technology,” said Chris Browy, vice president of sales/marketing at Avery. “Our strategic relationship with Xilinx on PCIe and CCIX enable us to deliver complete verification solutions to go along with Xilinx FPGA accelerator reference designs utilizing the new CCIX, PCIe 4.0, CHI interconnect IPs, and cache coherent, multi-core ARM processors. Our customers can develop new products more confidently and quickly knowing a SystemVerilog/UVM reference verification environment is available for their target FPGA platform.”

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI Express, CCIX, USB, AMBA, UFS, Unipro, CSI-2/DSI-2, Soundwire, Sensewire, DDR/LPDDR, HBM, HMC, ONFI/Toggle, NVM Express, SAS, SATA, eMMC, SD/SDIO, CAN FD, LIN, FlexRay, HDMI, and DisplayPort standards. The company is a member of the Mentor Graphics Value Added Partnership (VAP) program and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.


Avery Design Systems
Chris Browy, 978-851-3627
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