SUNNYVALE, Calif. – July 8, 2013 – Real Intent, Inc., a leading provider of EDA advanced sign-off verification solutions, today announced it has joined the Synopsys in-Sync™ program for two of its flows – the Synopsys VCS® Verilog simulator tie-in to Real Intent’s Ascent™ and Meridian™ products; and the Synopsys HDL Compiler™ tool flow tie-in to its Meridian products.
“Since our beginning, Synopsys has advanced tool interoperability via standards organizations and our own programs including in-Sync,” said Karen Bartleson, senior director of Community Marketing at Synopsys, Inc. “By joining in-Sync, Real Intent can work with us in verification and synthesis to help our mutual customers meet their stringent design flow requirements."
CDC analysis and verification are vital at both the pre- and post-synthesis stages of design to ensure against signal metastability. Correct and complete CDC analysis and verification require a clean and correct SDC file that is also used in the synthesis, and timing analysis steps. The Meridian flow with HDL Compiler ensures compatibility for SDC files. The tie-in of VCS to Ascent and Meridian products provides dynamic verification of both X-propagation and metastability issues.
Graham Bell, vice president of Marketing at Real Intent said, “Our solutions play well with others in the industry, and we are especially pleased to become a member of Synopsys’ in-Sync Program. Our membership provides access to Synopsys’ market-leading verification and synthesis technologies to ensure interoperability, and brings time and cost efficiencies to our mutual customers who now can take advantage of a proven and qualified design flow.”
About Real Intent
Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. The company provides comprehensive CDC verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. Real Intent’s Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness. Please visit www.realintent.com for more information.
ASIC: Application-Specific Integrated Circuit
CDC: Clock Domain Crossing
EDA: Electronic Design Automation
FPGA: Field-Programmable Gate Array
HDL: Hardware Description Language
RTL: Register Transfer Level
SDC: Synopsys Design Constraints
Ascent and Meridian are trademarks of Real Intent, Inc.
All other trademarks and trade names are the property of their respective owners.
Sarah Miller for Real Intent
ThinkBold Corporate Communications